top.v

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· Verilog 代码 · 共 89 行

//**************************************************************************************************/
//*  $Id: GS0521803	dandan
//*
//*      (C) COPYRIGHT 2006 Institute of Communication,Detecting and Controlling Technologies,BUAA
//*      CONFIDENTIAL AND PROPRIETARY.  ALL RIGHTS RESERVED.
//* 
//*      Responsible:   Lawrence Du
//*      Project:       EDA_Course
//**************************************************************************************************/
//---------------------------------------------top.v--------------------------------------------------------

module top(glbclk,shift,select,set,keyin,led_scan,led_out,o_light,alm_light,reset);

input  glbclk;        				//clk input:30M Hz
input  shift,         
       select,
       set; 
input  keyin;		  				//if it is 1, stop clock_alarm 
output reset;
output o_light;       				// if it is x o'clock, shining for 5 seconds
output alm_light;     				// alarm clock，if it is xx:xx, shining for 1 seconds

output[5:0] led_scan; 				//seven segment commom anode or cathode;
									//bit5为最高位,bit0为最低位 
output[7:0] led_out;  				// signal of seven segments and one dot;
									//bit0=g,bit1=f,bit2=e,bit3=d,bit4=c,bit5=b,bit6=a,bit7=dot

//////////////////////////////////////////////////////////////////////////////////////////////////////////////

									//调用time_screen_setm模块  date_screen_set模块
wire day_carry;
									//年计数器，月计数器，日计数器，小时计数器，分钟计数器，秒计数器
wire [7:0] year_count,month_count,day_count,hour_count,minute_count,sec_count;

									//调用clock_alarm_set模块
wire alm_light;						//闹钟显示灯
									//闹钟小时计数器，分钟计数器
wire [7:0] clock_h_count,clock_m_count;

									//调用second模块
									//秒表分钟，秒，百分秒计数器
wire [7:0] sec_m_count,sec_s_count,sec_ms_count;

									//调用o_alarm模块
wire o_light;						//整点报时显示灯

									//调用led模块
wire [5:0] led_scan;
wire [7:0] led_out;

									// 调用分频器
wire clk_1000,clk_100,clk_5,clk_1;

									//调用my_clock
wire [5:0] mode;
wire [1:0] screen_mode;
wire [2:0] mode_time;
wire [2:0] mode_date;
wire [2:0] mode_clock;
wire [2:0] mode_sec;
wire alm_light_on;					//闹钟开关
wire o_light_on;					//整点报时开关

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

my_clock mc(glbclk,shift,select,set,keyin,mode,screen_mode,mode_time,mode_date,mode_clock,mode_sec,
				alm_light_on,o_light_on,reset);

my_division  md(glbclk,reset,clk_1000,clk_100,clk_5,clk_1);

time_screen_set  tss(clk_5,reset,set,mode,mode_time,hour_count,minute_count,sec_count,day_carry);

date_screen_set  dss(clk_5,reset,set,day_carry,mode,mode_date,year_count,month_count,day_count);

clock_alarm_set cas(clk_5,reset,mode,mode_clock,set,keyin,alm_light_on,hour_count,minute_count,
						clock_h_count,clock_m_count,alm_light);

o_alarm  oa(clk_1,reset,minute_count,sec_count,o_light_on,o_light);

second s(clk_100,reset,mode,mode_sec,sec_m_count,sec_s_count,sec_ms_count);

led	l(glbclk,clk_1000,clk_100,clk_1,reset,mode,screen_mode,mode_time,mode_date,mode_clock,
			year_count,month_count,day_count,hour_count,minute_count,sec_count,
			clock_h_count,clock_m_count,sec_m_count,sec_s_count,sec_ms_count,
			alm_light_on,o_light_on,led_scan,led_out);
			
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

endmodule