transcript

一个电子中的verilog实验源代码。适合verilog初学者学习参考

# Reading D:/Modeltech_5.8d/tcl/vsim/pref.tcl 
# //  ModelSim SE 5.8d Jun 12 2004 
# //
# //  Copyright Model Technology, a Mentor Graphics Corporation company, 2004
# //                         All Rights Reserved.
# //                   UNPUBLISHED, LICENSED SOFTWARE.
# //         CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //        PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
#  OpenFile "E:/EDA_document/homework1/group01all/my_final_clock/my_clock_tb.v" 
vlib work
vmap work work
# Copying D:\Modeltech_5.8d\win32/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# Warning: Copied D:\Modeltech_5.8d\win32/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/add3.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module add3
# 
# Top level modules:
# 	add3
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/binary_to_BCD.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module binary_to_BCD
# 
# Top level modules:
# 	binary_to_BCD
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/clock_alarm_set.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module clock_alarm_set
# 
# Top level modules:
# 	clock_alarm_set
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/date_screen_set.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module date_screen_set
# 
# Top level modules:
# 	date_screen_set
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/division.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module division
# 
# Top level modules:
# 	division
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/led.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module led
# 
# Top level modules:
# 	led
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/my_clock.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module my_clock
# 
# Top level modules:
# 	my_clock
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/my_clock_tb.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module my_clock_tb
# 
# Top level modules:
# 	my_clock_tb
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/my_division.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module my_division
# 
# Top level modules:
# 	my_division
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/o_alarm.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module o_alarm
# 
# Top level modules:
# 	o_alarm
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/scan.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module scan
# 
# Top level modules:
# 	scan
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/second.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module second
# 
# Top level modules:
# 	second
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/time_screen_set.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module time_screen_set
# 
# Top level modules:
# 	time_screen_set
vlog -reportprogress 300 -work work E:/EDA_document/homework1/group01all/my_final_clock/top.v
# Model Technology ModelSim SE vlog 5.8d Compiler 2004.06 Jun 12 2004
# -- Compiling module top
# 
# Top level modules:
# 	top
vsim work.my_clock_tb
# vsim work.my_clock_tb 
# Loading work.my_clock_tb
# Loading work.top
# ** Warning: (vsim-3009) [TSCALE] - Module 'top' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t
# Loading work.my_clock
# ** Warning: (vsim-3009) [TSCALE] - Module 'my_clock' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/mc
# Loading work.my_division
# ** Warning: (vsim-3009) [TSCALE] - Module 'my_division' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/md
# Loading work.division
# Loading work.time_screen_set
# ** Warning: (vsim-3009) [TSCALE] - Module 'time_screen_set' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/tss
# Loading work.date_screen_set
# ** Warning: (vsim-3009) [TSCALE] - Module 'date_screen_set' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/dss
# Loading work.clock_alarm_set
# ** Warning: (vsim-3009) [TSCALE] - Module 'clock_alarm_set' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/cas
# Loading work.o_alarm
# ** Warning: (vsim-3009) [TSCALE] - Module 'o_alarm' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/oa
# Loading work.second
# ** Warning: (vsim-3009) [TSCALE] - Module 'second' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/s
# Loading work.led
# ** Warning: (vsim-3009) [TSCALE] - Module 'led' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/l
# Loading work.binary_to_BCD
# ** Warning: (vsim-3009) [TSCALE] - Module 'binary_to_BCD' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/l/b2b1
# Loading work.add3
# Loading work.scan
# ** Warning: (vsim-3009) [TSCALE] - Module 'scan' does not have a `timescale directive in effect, but previous modules do.
#         Region: /my_clock_tb/t/l/s
run 1us
# Break key hit 
# Break at E:/EDA_document/homework1/group01all/my_final_clock/add3.v line 21
run 1ns
run 50ns
# Break at E:/EDA_document/homework1/group01all/my_final_clock/my_clock_tb.v line 143