add3.v

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· Verilog 代码 · 共 36 行

// **********************************************************************************
// FileName		: add3.v
//
// Discription	:
//
// Date			: 
//
// Author		: dandan
// **********************************************************************************
`timescale 1ps/1ps
module add3(clk_i, rst_i, in, out);
input clk_i, rst_i;
input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @ (posedge clk_i)
	if (rst_i)
		out <= 4'b0000;
	else
		case (in)
		4'b0000: out <= 4'b0000;
		4'b0001: out <= 4'b0001;
		4'b0010: out <= 4'b0010;
		4'b0011: out <= 4'b0011;
		4'b0100: out <= 4'b0100;
		4'b0101: out <= 4'b1000;
		4'b0110: out <= 4'b1001;
		4'b0111: out <= 4'b1010;
		4'b1000: out <= 4'b1011;
		4'b1001: out <= 4'b1100;
		default: out <= 4'b0000;
		endcase
endmodule