_primary.vhd

来自「一个电子中的verilog实验源代码。适合verilog初学者学习参考」· VHDL 代码 · 共 43 行

library verilog;
use verilog.vl_types.all;
entity my_clock is
    generic(
        Time_screen     : integer := 1;
        Time_set        : integer := 2;
        Date_set        : integer := 4;
        Clock_set       : integer := 8;
        Sec_clock       : integer := 16;
        O_light_set     : integer := 32;
        Screen_clock    : integer := 1;
        Screen_date     : integer := 2;
        Hour_set        : integer := 4;
        Minute_set      : integer := 2;
        Sec_set         : integer := 1;
        Day_set         : integer := 1;
        Month_set       : integer := 2;
        Year_set        : integer := 4;
        Clock_on        : integer := 4;
        Clock_hour      : integer := 2;
        Clock_minute    : integer := 1;
        Sec_on          : integer := 2;
        Sec_stop        : integer := 1;
        Sec_reset       : integer := 4
    );
    port(
        glbclk          : in     vl_logic;
        shift           : in     vl_logic;
        \select\        : in     vl_logic;
        set             : in     vl_logic;
        keyin           : in     vl_logic;
        mode            : out    vl_logic_vector(5 downto 0);
        screen_mode     : out    vl_logic_vector(1 downto 0);
        mode_time       : out    vl_logic_vector(2 downto 0);
        mode_date       : out    vl_logic_vector(2 downto 0);
        mode_clock      : out    vl_logic_vector(2 downto 0);
        mode_sec        : out    vl_logic_vector(2 downto 0);
        alm_light_on    : out    vl_logic;
        o_light_on      : out    vl_logic;
        reset           : out    vl_logic
    );
end my_clock;