hdpdeps.ref

来自「verilog 时钟程序实例在ise下编译通过spatan3的芯片」· REF 代码 · 共 6 行

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FL e:/clock/clock.vhd 2004/05/21.21:32:06
EN work/CLOCK           FL e:/clock/clock.vhd PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CLOCK/BEHAVIORAL FL e:/clock/clock.vhd EN work/CLOCK