m74148a.hier_info

采用verilog设计

|m74148a
ei => a2~0.OUTPUTSELECT
ei => a1~0.OUTPUTSELECT
ei => a0~0.OUTPUTSELECT
ei => gs~0.OUTPUTSELECT
ei => eo~0.OUTPUTSELECT
i0 => reduce_nor~0.IN7
i1 => reduce_nor~6.IN6
i1 => reduce_nor~0.IN6
i2 => reduce_nor~5.IN5
i2 => reduce_nor~6.IN5
i2 => reduce_nor~0.IN5
i3 => reduce_nor~4.IN4
i3 => reduce_nor~5.IN4
i3 => reduce_nor~6.IN4
i3 => reduce_nor~0.IN4
i4 => reduce_nor~3.IN3
i4 => reduce_nor~4.IN3
i4 => reduce_nor~5.IN3
i4 => reduce_nor~6.IN3
i4 => reduce_nor~0.IN3
i5 => reduce_nor~2.IN2
i5 => reduce_nor~3.IN2
i5 => reduce_nor~4.IN2
i5 => reduce_nor~5.IN2
i5 => reduce_nor~6.IN2
i5 => reduce_nor~0.IN2
i6 => reduce_nor~1.IN1
i6 => reduce_nor~2.IN1
i6 => reduce_nor~3.IN1
i6 => reduce_nor~4.IN1
i6 => reduce_nor~5.IN1
i6 => reduce_nor~6.IN1
i6 => reduce_nor~0.IN1
i7 => reduce_or~0.IN0
i7 => reduce_or~1.IN0
i7 => reduce_or~2.IN0
i7 => reduce_nor~2.IN0
i7 => reduce_nor~1.IN0
i7 => reduce_nor~3.IN0
i7 => reduce_nor~4.IN0
i7 => reduce_nor~5.IN0
i7 => reduce_nor~6.IN0
i7 => reduce_nor~0.IN0
a2 <= a2~0.DB_MAX_OUTPUT_PORT_TYPE
a1 <= a1~0.DB_MAX_OUTPUT_PORT_TYPE
a0 <= a0~0.DB_MAX_OUTPUT_PORT_TYPE
gs <= gs~0.DB_MAX_OUTPUT_PORT_TYPE
eo <= eo~0.DB_MAX_OUTPUT_PORT_TYPE