receive.par

自己在ISE下用VHDL写的UART

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

NEU-96YK9Y816SD::  Wed Apr 12 14:55:08 2006


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 receive_map.ncd
receive.ncd receive.pcf 


Constraints file: receive.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "receive_map.ncd".
   "receive" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10
Loading device for application Par from file '4vlx25.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.46 2004-07-09.


Device utilization summary:

   Number of External IOBs            11 out of 240     4%
      Number of LOCed External IOBs    0 out of 11      0%

   Number of Slices                   31 out of 10752   1%

   Number of BUFGs                     3 out of 32      9%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989723) REAL time: 9 secs 

.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 9 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 9 secs 

Phase 5.8
..
Phase 5.8 (Checksum:996e1f) REAL time: 9 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 9 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 10 secs 

Writing design to file receive.ncd.

Total REAL time to Placer completion: 10 secs 
Total CPU time to Placer completion: 8 secs 


Phase 1: 207 unrouted;       REAL time: 10 secs 

Phase 2: 184 unrouted;       REAL time: 18 secs 

Phase 3: 33 unrouted;       REAL time: 18 secs 

Phase 4: 0 unrouted;       REAL time: 18 secs 

Total REAL time to Router completion: 18 secs 
Total CPU time to Router completion: 16 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Max Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |BUFGCTRL_X| No   |    6 |  0.510     |  1.953      |
+-------------------------+----------+------+------+------------+-------------+
|            clkdiv       |BUFGCTRL_X| No   |   15 |  0.502     |  1.960      |
+-------------------------+----------+------+------+------------+-------------+
|         RXD_BUFGP       |BUFGCTRL_X| No   |   10 |  0.000     |  1.969      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 125


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.833
   The MAXIMUM PIN DELAY IS:                               3.787
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.082

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         160          35          11           1           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 19 secs 
Total CPU time to PAR completion: 17 secs 

Peak Memory Usage:  126 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file receive.ncd.


PAR done.