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Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file E:/sk/iseobject/ex/sk/receive.vhd in Library work.Entity <receive> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file E:/sk/iseobject/ex/sk/send.vhd in Library work.Entity <send> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file E:/sk/iseobject/ex/sk/ctrl.vhd in Library work.Entity <ctrl> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View VHDL Functional Model".Release 6.3i - sch2vhdl G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 36 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file E:/sk/iseobject/ex/sk/receive.vhd in Library work.Architecture behavioral of Entity receive is up to date.Compiling vhdl file E:/sk/iseobject/ex/sk/send.vhd in Library work.Architecture behavioral of Entity send is up to date.Compiling vhdl file E:/sk/iseobject/ex/sk/ctrl.vhd in Library work.Architecture behavioral of Entity ctrl is up to date.Compiling vhdl file e:/sk/iseobject/ex/new_top.vhf in Library work.Entity <new_top> (Architecture <BEHAVIORAL>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <new_top> (Architecture <BEHAVIORAL>).Entity <new_top> analyzed. Unit <new_top> generated.Analyzing Entity <receive> (Architecture <behavioral>).Entity <receive> analyzed. Unit <receive> generated.Analyzing Entity <send> (Architecture <behavioral>).Entity <send> analyzed. Unit <send> generated.Analyzing Entity <ctrl> (Architecture <behavioral>).WARNING:Xst:819 - E:/sk/iseobject/ex/sk/ctrl.vhd line 43: The following signals are missing in the process sensitivity list: rst.WARNING:Xst:819 - E:/sk/iseobject/ex/sk/ctrl.vhd line 62: The following signals are missing in the process sensitivity list: rst.Entity <ctrl> analyzed. Unit <ctrl> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <ctrl>. Related source file is E:/sk/iseobject/ex/sk/ctrl.vhd. Found 1-bit register for signal <d1>. Found 1-bit register for signal <d2>. Found 1-bit register for signal <t1>. Found 1-bit register for signal <t2>. Found 1-bit register for signal <t3>. Found 8-bit register for signal <tmp_data>. Found 1-bit register for signal <tmp_load>. Summary: inferred 14 D-type flip-flop(s).Unit <ctrl> synthesized.Synthesizing Unit <send>. Related source file is E:/sk/iseobject/ex/sk/send.vhd. Found finite state machine <FSM_0> for signal <c>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 10 | | Inputs | 0 | | Outputs | 10 | | Clock | clkdiv (rising_edge) | | Clock enable | flag3 (positive) | | Power Up State | 0000000001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <busy>. Found 1-bit register for signal <clkdiv>. Found 10-bit up counter for signal <count>. Found 8-bit register for signal <databuffer>. Found 1-bit register for signal <flag1>. Found 1-bit register for signal <flag2>. Found 1-bit xor2 for signal <flag3>. Found 1-bit register for signal <t>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 13 D-type flip-flop(s).Unit <send> synthesized.Synthesizing Unit <receive>. Related source file is E:/sk/iseobject/ex/sk/receive.vhd.WARNING:Xst:653 - Signal <f4> is used but never assigned. Tied to value 0.WARNING:Xst:653 - Signal <f5> is used but never assigned. Tied to value 0.WARNING:Xst:646 - Signal <f6> is assigned but never used. Found finite state machine <FSM_1> for signal <c>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 10 | | Inputs | 0 | | Outputs | 10 | | Clock | clkdiv (rising_edge) | | Clock enable | f3 (positive) | | Power Up State | 0000000001 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <do>. Found 8-bit register for signal <data>. Found 1-bit register for signal <clkdiv>. Found 10-bit up counter for signal <count>. Found 1-bit register for signal <f1>. Found 1-bit register for signal <f2>. Found 1-bit xor2 for signal <f3>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 12 D-type flip-flop(s).Unit <receive> synthesized.Synthesizing Unit <new_top>. Related source file is e:/sk/iseobject/ex/new_top.vhf.Unit <new_top> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...MAC inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...DSP optimizations ...Selecting encoding for FSM_1 ...Optimizing FSM <FSM_1> on signal <c> with one-hot encoding.Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <c> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 2# Counters : 2 10-bit up counter : 2# Registers : 45 1-bit register : 43 8-bit register : 2# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <new_top> ...Optimizing unit <receive> ...Optimizing unit <send> ...Loading device for application Xst from file '4vlx25.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block new_top, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 4vlx25sf363-10 Number of Slices: 56 out of 10752 0% Number of Slice Flip Flops: 79 out of 21504 0% Number of 4 input LUTs: 81 out of 21504 0% Number of bonded IOBs: 3 out of 242 1% Number of GCLKs: 3 out of 32 9% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+XLXI_2_clkdiv:Q | NONE | 13 |clk100m | BUFGP | 36 |XLXI_1_clkdiv:Q | BUFG | 20 |rxd | BUFGP | 1 |XLXI_3_t3:Q | NONE | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -10 Minimum period: 4.430ns (Maximum Frequency: 225.749MHz) Minimum input arrival time before clock: 2.684ns Maximum output required time after clock: 3.951ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\sk\iseobject\ex/_ngo -i -pxc4vlx25-sf363-10 new_top.ngc new_top.ngd Reading NGO file "e:/sk/iseobject/ex/new_top.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 54316 kilobytesWriting NGD file "new_top.ngd" ...Writing NGDBUILD log file "new_top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "4vlx25sf363-10".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 2Logic Utilization: Number of Slice Flip Flops: 77 out of 21,504 1% Number of 4 input LUTs: 58 out of 21,504 1%Logic Distribution: Number of occupied Slices: 63 out of 10,752 1% Number of Slices containing only related logic: 63 out of 63 100% Number of Slices containing unrelated logic: 0 out of 63 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 68 out of 21,504 1% Number used as logic: 58 Number used as a route-thru: 10 Number of bonded IOBs: 5 out of 240 2% Number of BUFG/BUFGCTRLs: 3 out of 32 9% Number used as BUFGs: 3 Number used as BUFGCTRLs: 0Total equivalent gate count for design: 1,088Additional JTAG gate count for IOBs: 240Peak Memory Usage: 123 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "new_top_map.mrp" for details.Completed process "Map".Mapping Module new_top . . .
MAP command line:
map -intstyle ise -p xc4vlx25-sf363-10 -cm area -pr b -k 4 -c 100 -tx off -o new_top_map.ncd new_top.ngd new_top.pcf
Mapping Module new_top: DONE
Started process "Place & Route".Constraints file: new_top.pcfWARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 36 days, this program will not operate. For more information about thisproduct, please refer to the Evaluation Agreement, which was shipped toyou along with⌨️ 快捷键说明
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