ex.npl

自己在ISE下用VHDL写的UART

JDF G
// Created by Project Navigator ver 1.0
PROJECT ex
DESIGN ex
DEVFAM virtex4
DEVFAMTIME 0
DEVICE xc4vlx25
DEVICETIME 0
DEVPKG sf363
DEVPKGTIME 0
DEVSPEED -10
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE E:\sk\iseobject\ex\sk\send.vhd
SOURCE E:\sk\iseobject\ex\sk\receive.vhd
STIMULUS E:\sk\iseobject\ex\sk\rec_tb.vhd
SOURCE E:\sk\iseobject\ex\sk\ctrl.vhd
SOURCE E:\sk\iseobject\ex\sk\new_top.sch
STIMULUS E:\sk\iseobject\ex\sk\new_tb.vhd
STIMULUS send_tb.vhd
DEPASSOC new_top E:\sk\iseobject\ex\sk\u.ucf
[STATUS-ALL]
new_top.ncdFile=WARNINGS,1144827193
new_top.ngcFile=WARNINGS,1144824582
receive.ncdFile=WARNINGS,1144824908
receive.ngcFile=WARNINGS,1144824849
send.ncdFile=WARNINGS,1144825089
send.ngcFile=WARNINGS,1144825034
[STRATEGY-LIST]
Normal=True