transcript

自己在ISE下用VHDL写的UART

# Reading D:/Modeltech_6.0d/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0d Apr 25 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do testbench6.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity receive
# -- Compiling architecture behavioral of receive
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity send
# -- Compiling architecture behavioral of send
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity ctrl
# -- Compiling architecture behavioral of ctrl
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity new_top
# -- Compiling architecture behavioral of new_top
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Compiling entity testbench6
# -- Compiling architecture behavioral of testbench6
# vsim -lib work -t 1ps testbench6 
# Loading d:\Modeltech_6.0d\win32/../std.standard
# Loading d:\Modeltech_6.0d\win32/../ieee.std_logic_1164(body)
# Loading d:\Modeltech_6.0d\win32/../ieee.numeric_std(body)
# Loading d:\Modeltech_6.0d\win32/../std.textio(body)
# Loading d:\Modeltech_6.0d\win32/../ieee.vital_timing(body)
# Loading d:\simlib\EDK6.3_mti_se_nt\ISE_Lib\unisim.vcomponents
# Loading work.testbench6(behavioral)
# Loading work.new_top(behavioral)
# Loading d:\Modeltech_6.0d\win32/../ieee.std_logic_arith(body)
# Loading d:\Modeltech_6.0d\win32/../ieee.std_logic_unsigned(body)
# Loading work.receive(behavioral)
# Loading work.send(behavioral)
# Loading work.ctrl(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
run 200 us