new_top_timesim.nlf

自己在ISE下用VHDL写的UART

Release 6.3i - netgen G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Loading device database for application netgen from file "new_top.ncd".
   "new_top" is an NCD, version 2.38, device xc4vlx25, package sf363, speed -10
Loading device for application netgen from file '4vlx25.nph' in environment
D:/Xilinx.
Loading constraints from file "new_top.pcf"...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist new_top_timesim.vhd ...
Writing VHDL SDF file new_top_timesim.sdf ...
Total memory usage is 128544 kilobytes