receive.twr

自己在ISE下用VHDL写的UART

--------------------------------------------------------------------------------
Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml receive receive.ncd -o
receive.twr receive.pcf


Design file:              receive.ncd
Physical constraint file: receive.pcf
Device,speed:             xc4vlx25,-10 (PREVIEW 1.46 2004-07-09)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock RXD
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
RXD            |         |         |         |    3.271|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
RXD            |         |    4.344|         |         |
clk            |    5.517|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Apr 12 14:55:36 2006
--------------------------------------------------------------------------------

Peak Memory Usage: 115 MB