new_top.syr

自己在ISE下用VHDL写的UART

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.06 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: new_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : new_top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : new_top
Output Format                      : NGC
Target Device                      : xc4vlx25-10-sf363

---- Source Options
Top Module Name                    : new_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Map on DSP48                       : auto
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : new_top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/sk/iseobject/ex/sk/receive.vhd in Library work.
Architecture behavioral of Entity receive is up to date.
Compiling vhdl file E:/sk/iseobject/ex/sk/send.vhd in Library work.
Architecture behavioral of Entity send is up to date.
Compiling vhdl file E:/sk/iseobject/ex/sk/ctrl.vhd in Library work.
Architecture behavioral of Entity ctrl is up to date.
Compiling vhdl file e:/sk/iseobject/ex/new_top.vhf in Library work.
Entity <new_top> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <new_top> (Architecture <BEHAVIORAL>).
Entity <new_top> analyzed. Unit <new_top> generated.

Analyzing Entity <receive> (Architecture <behavioral>).
Entity <receive> analyzed. Unit <receive> generated.

Analyzing Entity <send> (Architecture <behavioral>).
Entity <send> analyzed. Unit <send> generated.

Analyzing Entity <ctrl> (Architecture <behavioral>).
WARNING:Xst:819 - E:/sk/iseobject/ex/sk/ctrl.vhd line 43: The following signals are missing in the process sensitivity list:
   rst.
WARNING:Xst:819 - E:/sk/iseobject/ex/sk/ctrl.vhd line 62: The following signals are missing in the process sensitivity list:
   rst.
Entity <ctrl> analyzed. Unit <ctrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ctrl>.
    Related source file is E:/sk/iseobject/ex/sk/ctrl.vhd.
    Found 1-bit register for signal <d1>.
    Found 1-bit register for signal <d2>.
    Found 1-bit register for signal <t1>.
    Found 1-bit register for signal <t2>.
    Found 1-bit register for signal <t3>.
    Found 8-bit register for signal <tmp_data>.
    Found 1-bit register for signal <tmp_load>.
    Summary:
	inferred  14 D-type flip-flop(s).
Unit <ctrl> synthesized.


Synthesizing Unit <send>.
    Related source file is E:/sk/iseobject/ex/sk/send.vhd.
    Found finite state machine <FSM_0> for signal <c>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 10                                             |
    | Clock              | clkdiv (rising_edge)                           |
    | Clock enable       | flag3 (positive)                               |
    | Power Up State     | 0000000001                                     |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <count>.
    Found 8-bit register for signal <databuffer>.
    Found 1-bit register for signal <flag1>.
    Found 1-bit register for signal <flag2>.
    Found 1-bit xor2 for signal <flag3>.
    Found 1-bit register for signal <t>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  13 D-type flip-flop(s).
Unit <send> synthesized.


Synthesizing Unit <receive>.
    Related source file is E:/sk/iseobject/ex/sk/receive.vhd.
WARNING:Xst:653 - Signal <f4> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <f5> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <f6> is assigned but never used.
    Found finite state machine <FSM_1> for signal <c>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 10                                             |
    | Clock              | clkdiv (rising_edge)                           |
    | Clock enable       | f3 (positive)                                  |
    | Power Up State     | 0000000001                                     |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <do>.
    Found 8-bit register for signal <data>.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <count>.
    Found 1-bit register for signal <f1>.
    Found 1-bit register for signal <f2>.
    Found 1-bit xor2 for signal <f3>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
Unit <receive> synthesized.


Synthesizing Unit <new_top>.
    Related source file is e:/sk/iseobject/ex/new_top.vhf.
Unit <new_top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <c> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Counters                         : 2
 10-bit up counter                 : 2
# Registers                        : 45
 1-bit register                    : 43
 8-bit register                    : 2
# Xors                             : 2
 1-bit xor2                        : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <new_top> ...

Optimizing unit <receive> ...

Optimizing unit <send> ...
Loading device for application Xst from file '4vlx25.nph' in environment D:/Xilinx.