testbench6.tdo

自己在ISE下用VHDL写的UART

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module new_top
vcom -87 -explicit  new_top_timesim.vhd
vcom -93 -explicit  E:/sk/iseobject/ex/sk/new_tb.vhd
vsim -t 1ps -sdfmax /UUT=new_top_timesim.sdf  -lib work testbench6
do testbench6.udo
view wave
add wave *
view structure
view signals
run 1000ns
## End