new_top.vhf

自己在ISE下用VHDL写的UART

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : new_top.vhf
-- /___/   /\     Timestamp : 04/12/2006 14:47:28
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: new_top
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity new_top is
   port ( clk100m : in    std_logic; 
          rst     : in    std_logic; 
          rxd     : in    std_logic; 
          busy    : out   std_logic; 
          txd     : out   std_logic);
end new_top;

architecture BEHAVIORAL of new_top is
   signal XLXN_18 : std_logic_vector (7 downto 0);
   signal XLXN_19 : std_logic_vector (7 downto 0);
   signal XLXN_20 : std_logic;
   signal XLXN_21 : std_logic;
   component receive
      port ( RXD  : in    std_logic; 
             clk  : in    std_logic; 
             do   : out   std_logic; 
             data : out   std_logic_vector (7 downto 0));
   end component;
   
   component send
      port ( load : in    std_logic; 
             clk  : in    std_logic; 
             data : in    std_logic_vector (7 downto 0); 
             TXD  : out   std_logic; 
             busy : out   std_logic);
   end component;
   
   component ctrl
      port ( clk100m  : in    std_logic; 
             do       : in    std_logic; 
             rst      : in    std_logic; 
             data_in  : in    std_logic_vector (7 downto 0); 
             load     : out   std_logic; 
             data_out : out   std_logic_vector (7 downto 0));
   end component;
   
begin
   XLXI_1 : receive
      port map (clk=>clk100m,      
                RXD=>rxd,      
                data(7 downto 0)=>XLXN_18(7 downto 0),      
                do=>XLXN_20);
   
   XLXI_2 : send
      port map (clk=>clk100m,      
                data(7 downto 0)=>XLXN_19(7 downto 0),      
                load=>XLXN_21,      
                busy=>busy,      
                TXD=>txd);
   
   XLXI_3 : ctrl
      port map (clk100m=>clk100m,      
                data_in(7 downto 0)=>XLXN_18(7 downto 0),      
                do=>XLXN_20,      
                rst=>rst,      
                data_out(7 downto 0)=>XLXN_19(7 downto 0),      
                load=>XLXN_21);
   
end BEHAVIORAL;