send_tb.vhd

自己在ISE下用VHDL写的UART

-- VHDL Test Bench Created from source file send.vhd -- 16:45:38 04/12/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY send_send_tb_vhd_tb IS
END send_send_tb_vhd_tb;

ARCHITECTURE behavior OF send_send_tb_vhd_tb IS 

	COMPONENT send
	PORT(
		data : IN std_logic_vector(7 downto 0);
		load : IN std_logic;
		clk : IN std_logic;          
		TXD : OUT std_logic;
		busy : OUT std_logic
		);
	END COMPONENT;

	SIGNAL TXD :  std_logic;
	SIGNAL busy :  std_logic;
	SIGNAL data :  std_logic_vector(7 downto 0);
	SIGNAL load :  std_logic;
	SIGNAL clk :  std_logic;

BEGIN

	uut: send PORT MAP(
		TXD => TXD,
		busy => busy,
		data => data,
		load => load,
		clk => clk
	);


process
 begin
   clk<='1';
   wait for 5 ns;
   clk<='0';
   wait for 5 ns;
end process;

process
begin
  load<='0'; 
  data<="10101010";
  wait for 500 ns;
  load<='1';
  wait for 20 ns;	  
  load<='0';
  wait;
end process;
END;