fujieqiall.tan.rpt

用FPGA实现数字复接?肍PGA实现数字复接

; N/A           ; None        ; -13.700 ns ; c7   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -14.000 ns ; b7   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -14.100 ns ; b3   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -14.200 ns ; b6   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -14.800 ns ; a7   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -14.800 ns ; a6   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -15.000 ns ; b1   ; djhlatch:m12|sig_save ; ena      ;
; N/A           ; None        ; -15.100 ns ; c6   ; djhlatch:m12|sig_save ; ena      ;
+---------------+-------------+------------+------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon May 22 23:10:55 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fujieqiall -c fujieqiall
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "djhlatch:m12|sig_save" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "ena" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Clock "clk" Internal fmax is restricted to 125.0 MHz between source register "shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = LC1_B7; Fanout = 2; COMB Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
            Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.100 ns; Loc. = LC2_B7; Fanout = 2; COMB Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
            Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.300 ns; Loc. = LC3_B7; Fanout = 3; COMB Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
            Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC4_B7; Fanout = 1; COMB Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
            Info: Total cell delay = 2.100 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
            Info: - Longest clock path from clock "clk" to source register is 3.900 ns
                Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B7; Fanout = 2; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
                Info: Total cell delay = 1.900 ns ( 48.72 % )
                Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: + Micro clock to output delay of source is 0.900 ns
        Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "djhlatch:m12|sig_save" (data pin = "c6", clock pin = "ena") is 19.000 ns
    Info: + Longest pin to register delay is 22.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_79; Fanout = 1; PIN Node = 'c6'
        Info: 2: + IC(3.400 ns) + CELL(1.900 ns) = 8.400 ns; Loc. = LC3_A10; Fanout = 1; COMB Node = 'neimacs0:m3|mux_8:u1|Y~13'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 10.900 ns; Loc. = LC5_A10; Fanout = 1; COMB Node = 'neimacs0:m3|mux_8:u1|Y~14'
        Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 13.400 ns; Loc. = LC4_A10; Fanout = 1; COMB Node = 'neimacs0:m3|tri_gate0:u2|dout0~14'
        Info: 5: + IC(2.300 ns) + CELL(1.900 ns) = 17.600 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'andmen:m11|outp~99'
        Info: 6: + IC(2.500 ns) + CELL(1.900 ns) = 22.000 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12|sig_save'
        Info: Total cell delay = 12.600 ns ( 57.27 % )
        Info: Total interconnect delay = 9.400 ns ( 42.73 % )
    Info: + Micro setup delay of destination is 3.900 ns
    Info: - Shortest clock path from clock "ena" to destination register is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'ena'
        Info: 2: + IC(2.400 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12|sig_save'
        Info: Total cell delay = 4.500 ns ( 65.22 % )
        Info: Total interconnect delay = 2.400 ns ( 34.78 % )
Info: tco from clock "clk" to destination pin "S0" through register "shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]" is 13.700 ns
    Info: + Longest clock path from clock "clk" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 8.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
        Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC8_B5; Fanout = 2; COMB Node = 'shixusuccessful:m5|yimaqi:u3|Y0~60'
        Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.900 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'S0'
        Info: Total cell delay = 5.800 ns ( 65.17 % )
        Info: Total interconnect delay = 3.100 ns ( 34.83 % )
Info: th for register "djhlatch:m12|sig_save" (data pin = "c0", clock pin = "ena") is -9.100 ns
    Info: + Longest clock path from clock "ena" to destination register is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'ena'
        Info: 2: + IC(2.400 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12|sig_save'
        Info: Total cell delay = 4.500 ns ( 65.22 % )
        Info: Total interconnect delay = 2.400 ns ( 34.78 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'c0'
        Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC2_A10; Fanout = 1; COMB Node = 'neimacs0:m3|mux_8:u1|Y~12'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.400 ns; Loc. = LC4_A10; Fanout = 1; COMB Node = 'neimacs0:m3|tri_gate0:u2|dout0~14'
        Info: 4: + IC(2.300 ns) + CELL(1.900 ns) = 11.600 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'andmen:m11|outp~99'
        Info: 5: + IC(2.500 ns) + CELL(1.900 ns) = 16.000 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12|sig_save'
        Info: Total cell delay = 9.000 ns ( 56.25 % )
        Info: Total interconnect delay = 7.000 ns ( 43.75 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Mon May 22 23:10:59 2006
    Info: Elapsed time: 00:00:06