neimacs0.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 33 行

library ieee ;
use ieee.std_logic_1164.all ;

entity neimacs0 is
port(in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1:in	std_logic;
K3,K2,K1:in	std_logic;
sx0:in	std_logic;
out0:out   std_logic
);
end neimacs0;
architecture behv of neimacs0 is

component mux_8 is
port(D7,D6,D5,D4,D3,D2,D1,D0:in	std_logic;
D,C,B:in	std_logic;
Y:out   std_logic
);
end component ;

component tri_gate0 is
	port(din0,en:in	std_logic;
	dout0:out   std_logic
	);
end component ;

signal IO:std_logic;
begin
u1:mux_8  port map(in0_8,in0_7,in0_6,in0_5,in0_4,in0_3,in0_2,in0_1,K3,K2,K1,IO);
u2:tri_gate0 port map(IO,sx0,out0);
end behv;