fujieqiall.map.qmsg

用FPGA实现数字复接?肍PGA实现数字复接

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D2 mux_8.vhd(19) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(19): signal \"D2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D3 mux_8.vhd(20) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(20): signal \"D3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D4 mux_8.vhd(21) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(21): signal \"D4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D5 mux_8.vhd(22) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(22): signal \"D5\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D6 mux_8.vhd(23) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(23): signal \"D6\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D7 mux_8.vhd(24) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(24): signal \"D7\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "mux_8.vhd(25) " "Info (10425): VHDL Case Statement information at mux_8.vhd(25): OTHERS choice is never selected" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 25 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tri_gate0 neimacs0:m1\|tri_gate0:u2 " "Info: Elaborating entity \"tri_gate0\" for hierarchy \"neimacs0:m1\|tri_gate0:u2\"" {  } { { "neimacs0.vhd" "u2" { Text "F:/EDA/fujieqiall/neimacs0.vhd" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shixusuccessful shixusuccessful:m5 " "Info: Elaborating entity \"shixusuccessful\" for hierarchy \"shixusuccessful:m5\"" {  } { { "fujieqiall.vhd" "m5" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 61 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nand0_1 shixusuccessful:m5\|nand0_1:u1 " "Info: Elaborating entity \"nand0_1\" for hierarchy \"shixusuccessful:m5\|nand0_1:u1\"" {  } { { "shixusuccessful.vhd" "u1" { Text "F:/EDA/fujieqiall/shixusuccessful.vhd" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count32 shixusuccessful:m5\|count32:u2 " "Info: Elaborating entity \"count32\" for hierarchy \"shixusuccessful:m5\|count32:u2\"" {  } { { "shixusuccessful.vhd" "u2" { Text "F:/EDA/fujieqiall/shixusuccessful.vhd" 31 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "yimaqi shixusuccessful:m5\|yimaqi:u3 " "Info: Elaborating entity \"yimaqi\" for hierarchy \"shixusuccessful:m5\|yimaqi:u3\"" {  } { { "shixusuccessful.vhd" "u3" { Text "F:/EDA/fujieqiall/shixusuccessful.vhd" 32 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "yimaqi.vhd(22) " "Info (10425): VHDL Case Statement information at yimaqi.vhd(22): OTHERS choice is never selected" {  } { { "yimaqi.vhd" "" { Text "F:/EDA/fujieqiall/yimaqi.vhd" 22 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count16 count16:m6 " "Info: Elaborating entity \"count16\" for hierarchy \"count16:m6\"" {  } { { "fujieqiall.vhd" "m6" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "men men:m7 " "Info: Elaborating entity \"men\" for hierarchy \"men:m7\"" {  } { { "fujieqiall.vhd" "m7" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 64 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "andmen andmen:m11 " "Info: Elaborating entity \"andmen\" for hierarchy \"andmen:m11\"" {  } { { "fujieqiall.vhd" "m11" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "djhlatch djhlatch:m12 " "Info: Elaborating entity \"djhlatch\" for hierarchy \"djhlatch:m12\"" {  } { { "fujieqiall.vhd" "m12" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sig_save djhlatch.vhd(17) " "Warning (10492): VHDL Process Statement warning at djhlatch.vhd(17): signal \"sig_save\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "sig_save djhlatch.vhd(12) " "Warning (10631): VHDL Process Statement warning at djhlatch.vhd(12): signal or variable \"sig_save\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"sig_save\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "shixusuccessful:m5\|count32:u2\|count_5\[0\]~5 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"shixusuccessful:m5\|count32:u2\|count_5\[0\]~5\"" {  } { { "count32.vhd" "count_5\[0\]~5" { Text "F:/EDA/fujieqiall/count32.vhd" 16 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "count16:m6\|count_4\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"count16:m6\|count_4\[0\]~4\"" {  } { { "count16.vhd" "count_4\[0\]~4" { Text "F:/EDA/fujieqiall/count16.vhd" 16 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51sp2/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "34 " "Info: Implemented 34 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 22 23:10:18 2006 " "Info: Processing ended: Mon May 22 23:10:18 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}