fujieqiall.map.qmsg

用FPGA实现数字复接?肍PGA实现数字复接

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 22 23:10:01 2006 " "Info: Processing started: Mon May 22 23:10:01 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fujieqiall -c fujieqiall " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fujieqiall -c fujieqiall" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "andmen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file andmen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 andmen-behv " "Info: Found design unit 1: andmen-behv" {  } { { "andmen.vhd" "" { Text "F:/EDA/fujieqiall/andmen.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 andmen " "Info: Found entity 1: andmen" {  } { { "andmen.vhd" "" { Text "F:/EDA/fujieqiall/andmen.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count16-behv " "Info: Found design unit 1: count16-behv" {  } { { "count16.vhd" "" { Text "F:/EDA/fujieqiall/count16.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count16 " "Info: Found entity 1: count16" {  } { { "count16.vhd" "" { Text "F:/EDA/fujieqiall/count16.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count32-behv " "Info: Found design unit 1: count32-behv" {  } { { "count32.vhd" "" { Text "F:/EDA/fujieqiall/count32.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count32 " "Info: Found entity 1: count32" {  } { { "count32.vhd" "" { Text "F:/EDA/fujieqiall/count32.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "djhlatch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file djhlatch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 djhlatch-behv " "Info: Found design unit 1: djhlatch-behv" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 djhlatch " "Info: Found entity 1: djhlatch" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fujieqiall.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fujieqiall.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fujieqiall-behv " "Info: Found design unit 1: fujieqiall-behv" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fujieqiall " "Info: Found entity 1: fujieqiall" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "men.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file men.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 men-behv " "Info: Found design unit 1: men-behv" {  } { { "men.vhd" "" { Text "F:/EDA/fujieqiall/men.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 men " "Info: Found entity 1: men" {  } { { "men.vhd" "" { Text "F:/EDA/fujieqiall/men.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux_8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux_8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_8-behv " "Info: Found design unit 1: mux_8-behv" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux_8 " "Info: Found entity 1: mux_8" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nand0_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file nand0_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 nand0_1-behv " "Info: Found design unit 1: nand0_1-behv" {  } { { "nand0_1.vhd" "" { Text "F:/EDA/fujieqiall/nand0_1.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 nand0_1 " "Info: Found entity 1: nand0_1" {  } { { "nand0_1.vhd" "" { Text "F:/EDA/fujieqiall/nand0_1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "neimacs0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file neimacs0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neimacs0-behv " "Info: Found design unit 1: neimacs0-behv" {  } { { "neimacs0.vhd" "" { Text "F:/EDA/fujieqiall/neimacs0.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 neimacs0 " "Info: Found entity 1: neimacs0" {  } { { "neimacs0.vhd" "" { Text "F:/EDA/fujieqiall/neimacs0.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shixusuccessful.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shixusuccessful.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shixusuccessful-behv " "Info: Found design unit 1: shixusuccessful-behv" {  } { { "shixusuccessful.vhd" "" { Text "F:/EDA/fujieqiall/shixusuccessful.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 shixusuccessful " "Info: Found entity 1: shixusuccessful" {  } { { "shixusuccessful.vhd" "" { Text "F:/EDA/fujieqiall/shixusuccessful.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tri_gate0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tri_gate0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tri_gate0-behv " "Info: Found design unit 1: tri_gate0-behv" {  } { { "tri_gate0.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate0.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tri_gate0 " "Info: Found entity 1: tri_gate0" {  } { { "tri_gate0.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate0.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tri_gate1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tri_gate1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tri_gate1-behv " "Info: Found design unit 1: tri_gate1-behv" {  } { { "tri_gate1.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tri_gate1 " "Info: Found entity 1: tri_gate1" {  } { { "tri_gate1.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yimaqi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file yimaqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 yimaqi-behv " "Info: Found design unit 1: yimaqi-behv" {  } { { "yimaqi.vhd" "" { Text "F:/EDA/fujieqiall/yimaqi.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 yimaqi " "Info: Found entity 1: yimaqi" {  } { { "yimaqi.vhd" "" { Text "F:/EDA/fujieqiall/yimaqi.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fujieqiall " "Info: Elaborating entity \"fujieqiall\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "w8 fujieqiall.vhd(54) " "Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object \"w8\" declared but not used" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "w9 fujieqiall.vhd(54) " "Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object \"w9\" declared but not used" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "w10 fujieqiall.vhd(54) " "Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object \"w10\" declared but not used" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "w101 fujieqiall.vhd(54) " "Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object \"w101\" declared but not used" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "w11 fujieqiall.vhd(54) " "Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object \"w11\" declared but not used" {  } { { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neimacs0 neimacs0:m1 " "Info: Elaborating entity \"neimacs0\" for hierarchy \"neimacs0:m1\"" {  } { { "fujieqiall.vhd" "m1" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_8 neimacs0:m1\|mux_8:u1 " "Info: Elaborating entity \"mux_8\" for hierarchy \"neimacs0:m1\|mux_8:u1\"" {  } { { "neimacs0.vhd" "u1" { Text "F:/EDA/fujieqiall/neimacs0.vhd" 28 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D0 mux_8.vhd(17) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(17): signal \"D0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D1 mux_8.vhd(18) " "Warning (10492): VHDL Process Statement warning at mux_8.vhd(18): signal \"D1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}