fujieqiall.tan.qmsg

用FPGA实现数字复接?肍PGA实现数字复接

{ "Info" "ITDB_TSU_RESULT" "djhlatch:m12\|sig_save c6 ena 19.000 ns register " "Info: tsu for register \"djhlatch:m12\|sig_save\" (data pin = \"c6\", clock pin = \"ena\") is 19.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest pin register " "Info: + Longest pin to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns c6 1 PIN PIN_79 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_79; Fanout = 1; PIN Node = 'c6'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { c6 } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.900 ns) 8.400 ns neimacs0:m3\|mux_8:u1\|Y~13 2 COMB LC3_A10 1 " "Info: 2: + IC(3.400 ns) + CELL(1.900 ns) = 8.400 ns; Loc. = LC3_A10; Fanout = 1; COMB Node = 'neimacs0:m3\|mux_8:u1\|Y~13'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "5.300 ns" { c6 neimacs0:m3|mux_8:u1|Y~13 } "NODE_NAME" } "" } } { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.900 ns neimacs0:m3\|mux_8:u1\|Y~14 3 COMB LC5_A10 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 10.900 ns; Loc. = LC5_A10; Fanout = 1; COMB Node = 'neimacs0:m3\|mux_8:u1\|Y~14'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.500 ns" { neimacs0:m3|mux_8:u1|Y~13 neimacs0:m3|mux_8:u1|Y~14 } "NODE_NAME" } "" } } { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 13.400 ns neimacs0:m3\|tri_gate0:u2\|dout0~14 4 COMB LC4_A10 1 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 13.400 ns; Loc. = LC4_A10; Fanout = 1; COMB Node = 'neimacs0:m3\|tri_gate0:u2\|dout0~14'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.500 ns" { neimacs0:m3|mux_8:u1|Y~14 neimacs0:m3|tri_gate0:u2|dout0~14 } "NODE_NAME" } "" } } { "tri_gate0.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate0.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.900 ns) 17.600 ns andmen:m11\|outp~99 5 COMB LC1_A11 1 " "Info: 5: + IC(2.300 ns) + CELL(1.900 ns) = 17.600 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'andmen:m11\|outp~99'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "4.200 ns" { neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 } "NODE_NAME" } "" } } { "andmen.vhd" "" { Text "F:/EDA/fujieqiall/andmen.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.900 ns) 22.000 ns djhlatch:m12\|sig_save 6 REG LC4_B6 1 " "Info: 6: + IC(2.500 ns) + CELL(1.900 ns) = 22.000 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12\|sig_save'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "4.400 ns" { andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.600 ns ( 57.27 % ) " "Info: Total cell delay = 12.600 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.400 ns ( 42.73 % ) " "Info: Total interconnect delay = 9.400 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "22.000 ns" { c6 neimacs0:m3|mux_8:u1|Y~13 neimacs0:m3|mux_8:u1|Y~14 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "22.000 ns" { c6 c6~out neimacs0:m3|mux_8:u1|Y~13 neimacs0:m3|mux_8:u1|Y~14 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } { 0.000ns 0.000ns 3.400ns 0.600ns 0.600ns 2.300ns 2.500ns } { 0.000ns 3.100ns 1.900ns 1.900ns 1.900ns 1.900ns 1.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.900 ns + " "Info: + Micro setup delay of destination is 3.900 ns" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ena destination 6.900 ns - Shortest register " "Info: - Shortest clock path from clock \"ena\" to destination register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns ena 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'ena'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { ena } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.400 ns) 6.900 ns djhlatch:m12\|sig_save 2 REG LC4_B6 1 " "Info: 2: + IC(2.400 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12\|sig_save'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.800 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 65.22 % ) " "Info: Total cell delay = 4.500 ns ( 65.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 34.78 % ) " "Info: Total interconnect delay = 2.400 ns ( 34.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "6.900 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "6.900 ns" { ena ena~out djhlatch:m12|sig_save } { 0.000ns 0.000ns 2.400ns } { 0.000ns 3.100ns 1.400ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "22.000 ns" { c6 neimacs0:m3|mux_8:u1|Y~13 neimacs0:m3|mux_8:u1|Y~14 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "22.000 ns" { c6 c6~out neimacs0:m3|mux_8:u1|Y~13 neimacs0:m3|mux_8:u1|Y~14 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } { 0.000ns 0.000ns 3.400ns 0.600ns 0.600ns 2.300ns 2.500ns } { 0.000ns 3.100ns 1.900ns 1.900ns 1.900ns 1.900ns 1.900ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "6.900 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "6.900 ns" { ena ena~out djhlatch:m12|sig_save } { 0.000ns 0.000ns 2.400ns } { 0.000ns 3.100ns 1.400ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk S0 shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 13.700 ns register " "Info: tco from clock \"clk\" to destination pin \"S0\" through register \"shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" is 13.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_43 11 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { clk } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC5_B7 5 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.000 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.900 ns + Longest register pin " "Info: + Longest register to pin delay is 8.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC5_B7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B7; Fanout = 5; REG Node = 'shixusuccessful:m5\|count32:u2\|lpm_counter:count_5_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 3.800 ns shixusuccessful:m5\|yimaqi:u3\|Y0~60 2 COMB LC8_B5 2 " "Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC8_B5; Fanout = 2; COMB Node = 'shixusuccessful:m5\|yimaqi:u3\|Y0~60'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.800 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] shixusuccessful:m5|yimaqi:u3|Y0~60 } "NODE_NAME" } "" } } { "yimaqi.vhd" "" { Text "F:/EDA/fujieqiall/yimaqi.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.900 ns) 8.900 ns S0 3 PIN PIN_25 0 " "Info: 3: + IC(1.200 ns) + CELL(3.900 ns) = 8.900 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'S0'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "5.100 ns" { shixusuccessful:m5|yimaqi:u3|Y0~60 S0 } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 65.17 % ) " "Info: Total cell delay = 5.800 ns ( 65.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 34.83 % ) " "Info: Total interconnect delay = 3.100 ns ( 34.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "8.900 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] shixusuccessful:m5|yimaqi:u3|Y0~60 S0 } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "8.900 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] shixusuccessful:m5|yimaqi:u3|Y0~60 S0 } { 0.000ns 1.900ns 1.200ns } { 0.000ns 1.900ns 3.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.900 ns" { clk shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "3.900 ns" { clk clk~out shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "8.900 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] shixusuccessful:m5|yimaqi:u3|Y0~60 S0 } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "8.900 ns" { shixusuccessful:m5|count32:u2|lpm_counter:count_5_rtl_0|alt_counter_f10ke:wysi_counter|q[4] shixusuccessful:m5|yimaqi:u3|Y0~60 S0 } { 0.000ns 1.900ns 1.200ns } { 0.000ns 1.900ns 3.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "djhlatch:m12\|sig_save c0 ena -9.100 ns register " "Info: th for register \"djhlatch:m12\|sig_save\" (data pin = \"c0\", clock pin = \"ena\") is -9.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ena destination 6.900 ns + Longest register " "Info: + Longest clock path from clock \"ena\" to destination register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns ena 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'ena'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { ena } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.400 ns) 6.900 ns djhlatch:m12\|sig_save 2 REG LC4_B6 1 " "Info: 2: + IC(2.400 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12\|sig_save'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.800 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 65.22 % ) " "Info: Total cell delay = 4.500 ns ( 65.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 34.78 % ) " "Info: Total interconnect delay = 2.400 ns ( 34.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "6.900 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "6.900 ns" { ena ena~out djhlatch:m12|sig_save } { 0.000ns 0.000ns 2.400ns } { 0.000ns 3.100ns 1.400ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 16.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns c0 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'c0'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "" { c0 } "NODE_NAME" } "" } } { "fujieqiall.vhd" "" { Text "F:/EDA/fujieqiall/fujieqiall.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.400 ns) 4.900 ns neimacs0:m3\|mux_8:u1\|Y~12 2 COMB LC2_A10 1 " "Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC2_A10; Fanout = 1; COMB Node = 'neimacs0:m3\|mux_8:u1\|Y~12'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "3.000 ns" { c0 neimacs0:m3|mux_8:u1|Y~12 } "NODE_NAME" } "" } } { "mux_8.vhd" "" { Text "F:/EDA/fujieqiall/mux_8.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 7.400 ns neimacs0:m3\|tri_gate0:u2\|dout0~14 3 COMB LC4_A10 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.400 ns; Loc. = LC4_A10; Fanout = 1; COMB Node = 'neimacs0:m3\|tri_gate0:u2\|dout0~14'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "2.500 ns" { neimacs0:m3|mux_8:u1|Y~12 neimacs0:m3|tri_gate0:u2|dout0~14 } "NODE_NAME" } "" } } { "tri_gate0.vhd" "" { Text "F:/EDA/fujieqiall/tri_gate0.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.900 ns) 11.600 ns andmen:m11\|outp~99 4 COMB LC1_A11 1 " "Info: 4: + IC(2.300 ns) + CELL(1.900 ns) = 11.600 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'andmen:m11\|outp~99'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "4.200 ns" { neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 } "NODE_NAME" } "" } } { "andmen.vhd" "" { Text "F:/EDA/fujieqiall/andmen.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.900 ns) 16.000 ns djhlatch:m12\|sig_save 5 REG LC4_B6 1 " "Info: 5: + IC(2.500 ns) + CELL(1.900 ns) = 16.000 ns; Loc. = LC4_B6; Fanout = 1; REG Node = 'djhlatch:m12\|sig_save'" {  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "4.400 ns" { andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "djhlatch.vhd" "" { Text "F:/EDA/fujieqiall/djhlatch.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 56.25 % ) " "Info: Total cell delay = 9.000 ns ( 56.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 43.75 % ) " "Info: Total interconnect delay = 7.000 ns ( 43.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "16.000 ns" { c0 neimacs0:m3|mux_8:u1|Y~12 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "16.000 ns" { c0 c0~out neimacs0:m3|mux_8:u1|Y~12 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } { 0.000ns 0.000ns 1.600ns 0.600ns 2.300ns 2.500ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.900ns 1.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "6.900 ns" { ena djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "6.900 ns" { ena ena~out djhlatch:m12|sig_save } { 0.000ns 0.000ns 2.400ns } { 0.000ns 3.100ns 1.400ns } } } { "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51sp2/bin/Report_Window_01.qrpt" "Compiler" "fujieqiall" "UNKNOWN" "V1" "F:/EDA/fujieqiall/db/fujieqiall.quartus_db" { Floorplan "F:/EDA/fujieqiall/" "" "16.000 ns" { c0 neimacs0:m3|mux_8:u1|Y~12 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } "NODE_NAME" } "" } } { "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51sp2/bin/Technology_Viewer.qrui" "16.000 ns" { c0 c0~out neimacs0:m3|mux_8:u1|Y~12 neimacs0:m3|tri_gate0:u2|dout0~14 andmen:m11|outp~99 djhlatch:m12|sig_save } { 0.000ns 0.000ns 1.600ns 0.600ns 2.300ns 2.500ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.900ns 1.900ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 22 23:10:59 2006 " "Info: Processing ended: Mon May 22 23:10:59 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}