fujieqiall.map.rpt

用FPGA实现数字复接?肍PGA实现数字复接

; Parameter Name         ; Value             ; Type                                     ;
+------------------------+-------------------+------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                           ;
; LPM_WIDTH              ; 4                 ; Untyped                                  ;
; LPM_DIRECTION          ; UP                ; Untyped                                  ;
; LPM_MODULUS            ; 0                 ; Untyped                                  ;
; LPM_AVALUE             ; UNUSED            ; Untyped                                  ;
; LPM_SVALUE             ; UNUSED            ; Untyped                                  ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                                  ;
; DEVICE_FAMILY          ; FLEX10K           ; Untyped                                  ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                                  ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                       ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                       ;
; CARRY_CNT_EN           ; SMART             ; Untyped                                  ;
; LABWIDE_SCLR           ; ON                ; Untyped                                  ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                                  ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                                  ;
+------------------------+-------------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/EDA/fujieqiall/fujieqiall.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition
    Info: Processing started: Mon May 22 23:10:01 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fujieqiall -c fujieqiall
Info: Found 2 design units, including 1 entities, in source file andmen.vhd
    Info: Found design unit 1: andmen-behv
    Info: Found entity 1: andmen
Info: Found 2 design units, including 1 entities, in source file count16.vhd
    Info: Found design unit 1: count16-behv
    Info: Found entity 1: count16
Info: Found 2 design units, including 1 entities, in source file count32.vhd
    Info: Found design unit 1: count32-behv
    Info: Found entity 1: count32
Info: Found 2 design units, including 1 entities, in source file djhlatch.vhd
    Info: Found design unit 1: djhlatch-behv
    Info: Found entity 1: djhlatch
Info: Found 2 design units, including 1 entities, in source file fujieqiall.vhd
    Info: Found design unit 1: fujieqiall-behv
    Info: Found entity 1: fujieqiall
Info: Found 2 design units, including 1 entities, in source file men.vhd
    Info: Found design unit 1: men-behv
    Info: Found entity 1: men
Info: Found 2 design units, including 1 entities, in source file mux_8.vhd
    Info: Found design unit 1: mux_8-behv
    Info: Found entity 1: mux_8
Info: Found 2 design units, including 1 entities, in source file nand0_1.vhd
    Info: Found design unit 1: nand0_1-behv
    Info: Found entity 1: nand0_1
Info: Found 2 design units, including 1 entities, in source file neimacs0.vhd
    Info: Found design unit 1: neimacs0-behv
    Info: Found entity 1: neimacs0
Info: Found 2 design units, including 1 entities, in source file shixusuccessful.vhd
    Info: Found design unit 1: shixusuccessful-behv
    Info: Found entity 1: shixusuccessful
Info: Found 2 design units, including 1 entities, in source file tri_gate0.vhd
    Info: Found design unit 1: tri_gate0-behv
    Info: Found entity 1: tri_gate0
Info: Found 2 design units, including 1 entities, in source file tri_gate1.vhd
    Info: Found design unit 1: tri_gate1-behv
    Info: Found entity 1: tri_gate1
Info: Found 2 design units, including 1 entities, in source file yimaqi.vhd
    Info: Found design unit 1: yimaqi-behv
    Info: Found entity 1: yimaqi
Info: Elaborating entity "fujieqiall" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object "w8" declared but not used
Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object "w9" declared but not used
Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object "w10" declared but not used
Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object "w101" declared but not used
Info (10035): Verilog HDL or VHDL information at fujieqiall.vhd(54): object "w11" declared but not used
Info: Elaborating entity "neimacs0" for hierarchy "neimacs0:m1"
Info: Elaborating entity "mux_8" for hierarchy "neimacs0:m1|mux_8:u1"
Warning (10492): VHDL Process Statement warning at mux_8.vhd(17): signal "D0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(18): signal "D1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(19): signal "D2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(20): signal "D3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(21): signal "D4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(22): signal "D5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(23): signal "D6" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at mux_8.vhd(24): signal "D7" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at mux_8.vhd(25): OTHERS choice is never selected
Info: Elaborating entity "tri_gate0" for hierarchy "neimacs0:m1|tri_gate0:u2"
Info: Elaborating entity "shixusuccessful" for hierarchy "shixusuccessful:m5"
Info: Elaborating entity "nand0_1" for hierarchy "shixusuccessful:m5|nand0_1:u1"
Info: Elaborating entity "count32" for hierarchy "shixusuccessful:m5|count32:u2"
Info: Elaborating entity "yimaqi" for hierarchy "shixusuccessful:m5|yimaqi:u3"
Info (10425): VHDL Case Statement information at yimaqi.vhd(22): OTHERS choice is never selected
Info: Elaborating entity "count16" for hierarchy "count16:m6"
Info: Elaborating entity "men" for hierarchy "men:m7"
Info: Elaborating entity "andmen" for hierarchy "andmen:m11"
Info: Elaborating entity "djhlatch" for hierarchy "djhlatch:m12"
Warning (10492): VHDL Process Statement warning at djhlatch.vhd(17): signal "sig_save" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at djhlatch.vhd(12): signal or variable "sig_save" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "sig_save" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "shixusuccessful:m5|count32:u2|count_5[0]~5"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "count16:m6|count_4[0]~4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 34 input pins
    Info: Implemented 5 output pins
    Info: Implemented 34 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Mon May 22 23:10:18 2006
    Info: Elapsed time: 00:00:17