shixusuccessful.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 41 行

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity shixusuccessful is
	port(B:in	std_logic;
	S3,S2,S1,S0:out   std_logic
	);
end shixusuccessful ;
architecture behv of shixusuccessful is
component count32 is
	port(X1:in	std_logic;
	E,D,C,B,A:out   std_logic
	);
end component ;

component yimaqi is
	port(F1,F2:in	std_logic;
	Y3,Y2,Y1,Y0:out   std_logic
	);
end component ;

component nand0_1 is
	port(X2:in	std_logic;
	out2:out   std_logic
	);
end component ;
signal in1,in2,in3,in4,in5,in6,in7:std_logic;
begin
u1:nand0_1 port map(B,in1);
u2:count32  port map(in1,in2,in3);
u3:yimaqi 
port map(in2,in3,in4,in5,in6,in7);
u4:nand0_1 port map(in4,S0);
u5:nand0_1 port map(in5,S1);
u6:nand0_1 port map(in6,S2);
u7:nand0_1 port map(in7,S3);
end behv;