men.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 16 行

library ieee ;
use ieee.std_logic_1164.all ;

entity men is
port(in1:in	std_logic;
out1:out std_logic
);
end men ;
architecture behv of men is

begin
out1<=in1;
end behv;