tri_gate0.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 17 行

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity tri_gate0 is
	port(din0,en:in	std_logic;
	dout0:out   std_logic
	);
end tri_gate0;
architecture behv of tri_gate0 is
begin
dout0<=din0 when en='1' else
'1';
end behv;