nand0_1.vhd

用FPGA实现数字复接?肍PGA实现数字复接

library ieee ;
use ieee.std_logic_1164.all ;

entity nand0_1 is
	port(X2:in	std_logic;
	out2:out   std_logic
	);
end nand0_1 ;
architecture behv of nand0_1 is
begin
out2<=not X2;
end behv;