count32.vhd

来自「用FPGA实现数字复接?肍PGA实现数字复接」· VHDL 代码 · 共 30 行

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity count32 is
	port(X1:in	std_logic;
	E,D,C,B,A:out   std_logic
	);
end count32 ;
architecture behv of count32 is
	signal count_5:std_logic_vector(4 downto 0);
begin

	process(X1)
	begin
		if X1'event and X1='1' then
			if count_5= "11111" then
				count_5<= "00000";				
				else
				count_5<=count_5+1;
			end if;
		end if;
	end process;
A<=count_5(0);
B<=count_5(1);
C<=count_5(2);
D<=count_5(3);
E<=count_5(4);
end behv;