fujieqiall.fit.talkback.xml

用FPGA实现数字复接?肍PGA实现数字复接

<!--
This XML file (created on Mon May 22 23:10:38 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
	<nic_id>000c76594cd8</nic_id>
	<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 216</build>
	<service_pack_label>2</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_fit.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Mon May 22 23:10:38 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2019</cpu_freq>
	</cpu>
	<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/fujieqiall/fujieqiall</top_file>
<compilation_summary>
	<flow_status>Successful - Mon May 22 23:10:37 2006</flow_status>
	<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
	<revision_name>fujieqiall</revision_name>
	<top_level_entity_name>fujieqiall</top_level_entity_name>
	<family>FLEX10K</family>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>34 / 576 ( 6 % )</total_logic_elements>
	<total_pins>39 / 59 ( 66 % )</total_pins>
	<total_memory_bits>0 / 6,144 ( 0 % )</total_memory_bits>
	<device>EPF10K10LC84-3</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>39BD95AD</compile_id>
<resource_usage_summary>
	<rsc name="Registers" util="1" max=" 576 " type="int">8 </rsc>
	<rsc name="Total LABs" util="0" max=" 72 " type="int">0 </rsc>
	<rsc name="Logic elements in carry chains" type="int">8</rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="I/O pins" util="66" max=" 59 " type="int">39 </rsc>
	<rsc name="-- Clock pins" type="int">4</rsc>
	<rsc name="-- Dedicated input pins" util="225" max=" 4 " type="int">9 </rsc>
	<rsc name="Global signals" type="int">1</rsc>
	<rsc name="EABs" util="0" max=" 3 " type="int">0 </rsc>
	<rsc name="Total memory bits" util="0" max=" 6144 " type="int">0 </rsc>
	<rsc name="Total RAM block bits" util="0" max=" 6144 " type="int">0 </rsc>
	<rsc name="Maximum fan-out node" type="text">count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[0]</rsc>
	<rsc name="Maximum fan-out" type="int">13</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">count16:m6|lpm_counter:count_4_rtl_1|alt_counter_f10ke:wysi_counter|q[0]</rsc>
	<rsc name="Highest non-global fan-out" type="int">12</rsc>
	<rsc name="Total fan-out" type="int">114</rsc>
	<rsc name="Average fan-out" type="float">1.56</rsc>
</resource_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off fujieqiall -c fujieqiall</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<info>Info: Quartus II Fitter was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:11</info>
	<info>Info: Processing ended: Mon May 22 23:10:37 2006</info>
	<info>Info: Fitter routing operations ending: elapsed time is 00:00:00</info>
	<info>Info: Fitter routing operations beginning</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>AUTO</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Individual Logic Cells</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Output Enable</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>clk</name>
		<pin__>43</pin__>
		<fan_out>8</fan_out>
		<global>yes</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c2</name>
		<pin__>84</pin__>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c1</name>
		<pin__>2</pin__>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c3</name>
		<pin__>44</pin__>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c0</name>
		<pin__>42</pin__>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c5</name>
		<pin__>1</pin__>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c6</name>
		<pin__>79</pin__>
		<col.>24</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c7</name>
		<pin__>19</pin__>
		<row>A</row>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>c4</name>
		<pin__>6</pin__>
		<col.>4</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>a2</name>
		<pin__>80</pin__>
		<col.>23</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>a1</name>
		<pin__>73</pin__>
		<row>A</row>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>a3</name>
		<pin__>9</pin__>
		<col.>2</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>a0</name>
		<pin__>83</pin__>
		<col.>13</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>TTL</i_o_standard>
	</row>
	<row>
		<name>a5</name>
		<pin__>38</pin__>
		<col.>10</col.>
		<fan_out>1</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>