fujieqiall.tan.talkback.xml

用FPGA实现数字复接?肍PGA实现数字复接

<!--
This XML file (created on Mon May 22 23:10:59 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
	<nic_id>000c76594cd8</nic_id>
	<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 216</build>
	<service_pack_label>2</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Mon May 22 23:11:00 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2019</cpu_freq>
	</cpu>
	<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/fujieqiall/fujieqiall</top_file>
<compilation_summary>
	<flow_status>Successful - Mon May 22 23:10:59 2006</flow_status>
	<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
	<revision_name>fujieqiall</revision_name>
	<top_level_entity_name>fujieqiall</top_level_entity_name>
	<family>FLEX10K</family>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_logic_elements>34 / 576 ( 6 % )</total_logic_elements>
	<total_pins>39 / 59 ( 66 % )</total_pins>
	<total_memory_bits>0 / 6,144 ( 0 % )</total_memory_bits>
	<device>EPF10K10LC84-3</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>6E2E331</compile_id>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off fujieqiall -c fujieqiall</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis is analyzing one or more combinational loops as latches</warning>
	<warning>Warning: Node &quot;djhlatch:m12|sig_save&quot; is a latch</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:06</info>
	<info>Info: Processing ended: Mon May 22 23:10:59 2006</info>
	<info>Info: th for register &quot;djhlatch:m12|sig_save&quot; (data pin = &quot;c0&quot;, clock pin = &quot;ena&quot;) is -9.100 ns</info>
	<info>Info: - Shortest pin to register delay is 16.000 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>ena</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>19.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>13.700 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-9.100 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>Restricted to 125.00 MHz ( period = 8.000 ns )</actual>
	</clk>
</performance>
<compile_id>C92A368D</compile_id>
</talkback>