agc.fit.rpt

AGC verilog实现

; y_out[4]  ; Incomplete set of assignments ;
; y_out[5]  ; Incomplete set of assignments ;
; y_out[6]  ; Incomplete set of assignments ;
; y_out[7]  ; Incomplete set of assignments ;
; y_out[8]  ; Incomplete set of assignments ;
; y_out[9]  ; Incomplete set of assignments ;
; y_out[10] ; Incomplete set of assignments ;
; y_out[11] ; Incomplete set of assignments ;
; y_out[12] ; Incomplete set of assignments ;
; y_out[13] ; Incomplete set of assignments ;
; y_out[14] ; Incomplete set of assignments ;
; y_out[15] ; Incomplete set of assignments ;
; x_in[1]   ; Incomplete set of assignments ;
; x_in[0]   ; Incomplete set of assignments ;
; x_in[2]   ; Incomplete set of assignments ;
; x_in[3]   ; Incomplete set of assignments ;
; x_in[4]   ; Incomplete set of assignments ;
; x_in[5]   ; Incomplete set of assignments ;
; x_in[6]   ; Incomplete set of assignments ;
; x_in[7]   ; Incomplete set of assignments ;
; x_in[8]   ; Incomplete set of assignments ;
; x_in[9]   ; Incomplete set of assignments ;
; x_in[10]  ; Incomplete set of assignments ;
; x_in[11]  ; Incomplete set of assignments ;
; x_in[12]  ; Incomplete set of assignments ;
; x_in[13]  ; Incomplete set of assignments ;
; x_in[14]  ; Incomplete set of assignments ;
; x_in[15]  ; Incomplete set of assignments ;
; rst       ; Incomplete set of assignments ;
+-----------+-------------------------------+


+-----------------------------------------------------------+
; Incremental Compilation Preservation Summary              ;
+--------------------------------------+--------------------+
; Type                                 ; Value              ;
+--------------------------------------+--------------------+
; Placement (by node)                  ;                    ;
;     -- Requested                     ; 0 / 291 ( 0.00 % ) ;
;     -- Achieved                      ; 0 / 291 ( 0.00 % ) ;
;                                      ;                    ;
; Routing (by net)                     ;                    ;
;     -- Requested                     ; 0 / 0 ( 0.00 % )   ;
;     -- Achieved                      ; 0 / 0 ( 0.00 % )   ;
;                                      ;                    ;
; Number of Tiles locked to High-Speed ; 0                  ;
+--------------------------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                             ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Top                            ; 289     ; 0                 ; N/A                     ; Source File       ;
; hard_block:auto_generated_inst ; 2       ; 0                 ; N/A                     ; Source File       ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/altera/wiretx/agc/agc.pin.


+------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                              ;
+-----------------------------------------------------------------------------------+------------------------+
; Resource                                                                          ; Usage                  ;
+-----------------------------------------------------------------------------------+------------------------+
; ALUTs Used                                                                        ; 144 / 38,000 ( < 1 % ) ;
;     -- Combinational ALUTs                                                        ; 144 / 38,000 ( < 1 % ) ;
;     -- Memory ALUTs                                                               ; 0 / 19,000 ( 0 % )     ;
;     -- LUT_REGs                                                                   ; 0 / 38,000 ( 0 % )     ;
; Dedicated logic registers                                                         ; 0 / 38,000 ( 0 % )     ;
;                                                                                   ;                        ;
; Combinational ALUT usage by number of inputs                                      ;                        ;
;     -- 7 input functions                                                          ; 0                      ;
;     -- 6 input functions                                                          ; 3                      ;
;     -- 5 input functions                                                          ; 6                      ;
;     -- 4 input functions                                                          ; 37                     ;
;     -- <=3 input functions                                                        ; 98                     ;
;                                                                                   ;                        ;
; Combinational ALUTs by mode                                                       ;                        ;
;     -- normal mode                                                                ; 139                    ;
;     -- extended LUT mode                                                          ; 0                      ;
;     -- arithmetic mode                                                            ; 5                      ;
;     -- shared arithmetic mode                                                     ; 0                      ;
;                                                                                   ;                        ;
; Logic utilization                                                                 ; 147 / 38,000 ( < 1 % ) ;
;     -- Difficulty Clustering Design                                               ; Low                    ;
;     -- Combinational ALUT/register pairs used in final Placement                  ; 144                    ;
;         -- Combinational with no register                                         ; 144                    ;
;         -- Register only                                                          ; 0                      ;
;         -- Combinational with a register                                          ; 0                      ;
;     -- Estimated pairs recoverable by pairing ALUTs and registers as design grows ; 0                      ;
;     -- Estimated Combinational ALUT/register pairs unavailable                    ; 3                      ;