agc.map.qmsg

AGC verilog实现

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[34\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[34\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[35\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[35\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power1\[36\] agc.v(12) " "Info (10041): Inferred latch for \"x_power1\[36\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[0\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[0\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[1\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[1\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[2\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[2\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[3\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[3\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[4\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[4\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[5\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[5\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[6\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[6\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[7\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[7\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[8\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[8\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[9\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[9\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[10\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[10\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[11\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[11\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[12\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[12\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[13\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[13\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[14\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[14\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[15\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[15\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[16\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[16\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[17\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[17\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[18\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[18\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[19\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[19\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[20\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[20\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_power\[21\] agc.v(12) " "Info (10041): Inferred latch for \"x_power\[21\]\" at agc.v(12)" {  } { { "agc.v" "" { Text "E:/altera/wiretx/agc/agc.v" 12 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}