📄 agc.flow.rpt
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Flow report for agc
Thu Dec 01 22:19:28 2011
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+-----------------------------------------------+
; Flow Status ; Successful - Thu Dec 01 22:19:28 2011 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; agc ;
; Top-level Entity Name ; agc ;
; Family ; Stratix III ;
; Device ; EP3SE50F484C2 ;
; Timing Models ; Final ;
; Met timing requirements ; N/A ;
; Logic utilization ; < 1 % ;
; Combinational ALUTs ; 144 / 38,000 ( < 1 % ) ;
; Memory ALUTs ; 0 / 19,000 ( 0 % ) ;
; Dedicated logic registers ; 0 / 38,000 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 71 / 296 ( 24 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 5,455,872 ( 0 % ) ;
; DSP block 18-bit elements ; 0 / 384 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------+-----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/01/2011 22:18:24 ;
; Main task ; Compilation ;
; Revision Name ; agc ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 159214198574.132274910401652 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; IP_TOOL_NAME ; ALTFP_MULT ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 10.0 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; mymult.bsf ; -- ; -- ; -- ;
; MISC_FILE ; mymult_inst.v ; -- ; -- ; -- ;
; MISC_FILE ; mymult_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; mymult.inc ; -- ; -- ; -- ;
; MISC_FILE ; mymult.cmp ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.1V ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
+-------------------------------------+------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 227 MB ; 00:00:04 ;
; Fitter ; 00:00:22 ; 1.0 ; 353 MB ; 00:00:18 ;
; TimeQuest Timing Analyzer ; 00:00:16 ; 1.0 ; 264 MB ; 00:00:06 ;
; Assembler ; 00:00:16 ; 1.0 ; 303 MB ; 00:00:09 ;
; EDA Netlist Writer ; 00:00:03 ; 1.0 ; 194 MB ; 00:00:02 ;
; Total ; 00:01:04 ; -- ; -- ; 00:00:39 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; pryangw ; Windows XP ; 5.1 ; i686 ;
; Fitter ; pryangw ; Windows XP ; 5.1 ; i686 ;
; TimeQuest Timing Analyzer ; pryangw ; Windows XP ; 5.1 ; i686 ;
; Assembler ; pryangw ; Windows XP ; 5.1 ; i686 ;
; EDA Netlist Writer ; pryangw ; Windows XP ; 5.1 ; i686 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off agc -c agc
quartus_fit --read_settings_files=off --write_settings_files=off agc -c agc
quartus_sta agc -c agc
quartus_asm --read_settings_files=off --write_settings_files=off agc -c agc
quartus_eda --read_settings_files=off --write_settings_files=off agc -c agc
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