agc.sta.rpt

AGC verilog实现

TimeQuest Timing Analyzer report for agc
Thu Dec 01 22:19:20 2011
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow 1100mV 85C Model Fmax Summary
  6. Slow 1100mV 85C Model Setup Summary
  7. Slow 1100mV 85C Model Hold Summary
  8. Slow 1100mV 85C Model Recovery Summary
  9. Slow 1100mV 85C Model Removal Summary
 10. Slow 1100mV 85C Model Minimum Pulse Width Summary
 11. Setup Times
 12. Hold Times
 13. Clock to Output Times
 14. Minimum Clock to Output Times
 15. Propagation Delay
 16. Minimum Propagation Delay
 17. Slow 1100mV 85C Model Metastability Report
 18. Slow 1100mV 0C Model Fmax Summary
 19. Slow 1100mV 0C Model Setup Summary
 20. Slow 1100mV 0C Model Hold Summary
 21. Slow 1100mV 0C Model Recovery Summary
 22. Slow 1100mV 0C Model Removal Summary
 23. Slow 1100mV 0C Model Minimum Pulse Width Summary
 24. Setup Times
 25. Hold Times
 26. Clock to Output Times
 27. Minimum Clock to Output Times
 28. Propagation Delay
 29. Minimum Propagation Delay
 30. Slow 1100mV 0C Model Metastability Report
 31. Fast 1100mV 0C Model Setup Summary
 32. Fast 1100mV 0C Model Hold Summary
 33. Fast 1100mV 0C Model Recovery Summary
 34. Fast 1100mV 0C Model Removal Summary
 35. Fast 1100mV 0C Model Minimum Pulse Width Summary
 36. Setup Times
 37. Hold Times
 38. Clock to Output Times
 39. Minimum Clock to Output Times
 40. Propagation Delay
 41. Minimum Propagation Delay
 42. Fast 1100mV 0C Model Metastability Report
 43. Multicorner Timing Analysis Summary
 44. Setup Times
 45. Hold Times
 46. Clock to Output Times
 47. Minimum Clock to Output Times
 48. Progagation Delay
 49. Minimum Progagation Delay
 50. Board Trace Model Assignments
 51. Input Transition Times
 52. Slow Corner Signal Integrity Metrics
 53. Fast Corner Signal Integrity Metrics
 54. Setup Transfers
 55. Hold Transfers
 56. Recovery Transfers
 57. Removal Transfers
 58. Report TCCS
 59. Report RSKM
 60. Unconstrained Paths
 61. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition ;
; Revision Name      ; agc                                                             ;
; Device Family      ; Stratix III                                                     ;
; Device Name        ; EP3SE50F484C2                                                   ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Enabled                                                         ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; rst        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { rst } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+------------------------------------------------+
; Slow 1100mV 85C Model Fmax Summary             ;
+----------+-----------------+------------+------+
; Fmax     ; Restricted Fmax ; Clock Name ; Note ;
+----------+-----------------+------------+------+
; 93.7 MHz ; 93.7 MHz        ; rst        ;      ;
+----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-------------------------------------+
; Slow 1100mV 85C Model Setup Summary ;
+-------+--------+--------------------+
; Clock ; Slack  ; End Point TNS      ;
+-------+--------+--------------------+
; rst   ; -4.836 ; -180.460           ;
+-------+--------+--------------------+


+------------------------------------+
; Slow 1100mV 85C Model Hold Summary ;
+-------+--------+-------------------+
; Clock ; Slack  ; End Point TNS     ;
+-------+--------+-------------------+
; rst   ; -4.309 ; -148.342          ;
+-------+--------+-------------------+


+----------------------------------------+
; Slow 1100mV 85C Model Recovery Summary ;
+-------+--------+-----------------------+
; Clock ; Slack  ; End Point TNS         ;
+-------+--------+-----------------------+
; rst   ; -1.072 ; -34.646               ;
+-------+--------+-----------------------+


+---------------------------------------+
; Slow 1100mV 85C Model Removal Summary ;
+-------+--------+----------------------+
; Clock ; Slack  ; End Point TNS        ;
+-------+--------+----------------------+
; rst   ; -3.698 ; -130.017             ;
+-------+--------+----------------------+


+---------------------------------------------------+
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
+-------+--------+----------------------------------+
; Clock ; Slack  ; End Point TNS                    ;
+-------+--------+----------------------------------+
; rst   ; -3.339 ; -1055.391                        ;
+-------+--------+----------------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; rst       ; rst        ; 5.316 ; 5.245 ; Fall       ; rst             ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; rst       ; rst        ; -0.374 ; -0.310 ; Fall       ; rst             ;
+-----------+------------+--------+--------+------------+-----------------+


+--------------------------------------------------------------------------+
; Clock to Output Times                                                    ;
+------------+------------+--------+--------+------------+-----------------+
; Data Port  ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+------------+------------+--------+--------+------------+-----------------+
; power[*]   ; rst        ; 14.174 ; 13.947 ; Rise       ; rst             ;
;  power[0]  ; rst        ; 12.022 ; 11.972 ; Rise       ; rst             ;
;  power[1]  ; rst        ; 13.169 ; 13.050 ; Rise       ; rst             ;
;  power[2]  ; rst        ; 12.994 ; 12.847 ; Rise       ; rst             ;
;  power[3]  ; rst        ; 13.531 ; 13.421 ; Rise       ; rst             ;
;  power[4]  ; rst        ; 14.174 ; 13.947 ; Rise       ; rst             ;