automake.log

在xilinx的ise环境下用vhdl编写的一个时钟程序。

ISE Auto-Make Log File
-----------------------

Updating: Configure Device (iMPACT)

Starting: 'exewrap @__clock_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/xilinx_webpack/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr'


Starting: 'D:/xilinx_webpack/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : clock.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-5
Output File Name                   : clock
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 5

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : clock.prj
Compiling included source file 'clock.v'
Module <clock> compiled.
Continuing compilation of source file 'clock.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'clock.prj'
No errors in compilation
Analysis of file <clock.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <clock>.
WARNING:Xst:854 - "clock.v", line 12: Ignored initial statement.
WARNING:Xst:905 - "clock.v", line 30: The signals <sec> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 36: The signals <min> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 46: The signals <count, sec> are missing in the sensitivity list of always block.
Module <clock> is correct for synthesis.

Synthesizing Unit <clock>.
    Related source file is clock.v.
WARNING:Xst:737 - Found 1-bit latch for signal <keyen_reg>.
    Found 16x8-bit ROM for internal node.
    Found 4-bit adder for signal <$n0000> created at line 85.
    Found 4-bit adder for signal <$n0001> created at line 89.
    Found 4-bit adder for signal <$n0002> created at line 93.
    Found 4-bit adder for signal <$n0003> created at line 97.
    Found 30-bit adder for signal <$old_count_1>.
    Found 30-bit register for signal <count>.
    Found 4-bit 4-to-1 multiplexer for signal <ledbuf>.
    Found 16-bit register for signal <min>.
    Found 1-bit register for signal <sec>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred  47 D-type flip-flop(s).
	inferred   1 Latch(s).
	inferred   5 Adder/Subtracter(s).
	inferred  12 Multiplexer(s).
Unit <clock> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  30-bit register                  : 1
  1-bit register                   : 17
# Latches                          : 1
  1-bit latch                      : 1
# Multiplexers                     : 2
  4-bit 4-to-1 multiplexer         : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  30-bit adder                     : 1

=========================================================================


Starting low level synthesis...
Optimizing unit <clock> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : clock
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  30-bit register                  : 1
  1-bit register                   : 17
# Multiplexers                     : 1
  4-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  30-bit adder                     : 1

Design Statistics
# IOs                              : 15

Cell Usage :
# BELS                             : 178
#      GND                         : 1
#      LUT1                        : 27
#      LUT1_D                      : 1
#      LUT1_L                      : 16
#      LUT2                        : 11
#      LUT3                        : 10
#      LUT4                        : 22
#      LUT4_D                      : 1
#      LUT4_L                      : 1
#      MUXCY                       : 41
#      MUXF5                       : 5
#      VCC                         : 1
#      XORCY                       : 41
# FlipFlops/Latches                : 48
#      FDE_1                       : 1
#      FDR_1                       : 30
#      FDRE_1                      : 16
#      LD                          : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 2
#      OBUF                        : 12
=========================================================================