clock.npl

来自「在xilinx的ise环境下用vhdl编写的一个时钟程序。」· NPL 代码 · 共 17 行

JDF E
// Created by ISE ver 1.0
PROJECT clock
DESIGN clock Normal
DEVKIT xc2s100-5pq208
DEVFAM spartan2
FLOW XST Verilog
MODULE clock.v
MODSTYLE clock Normal

[STRATEGY-LIST]
Normal=True, 1046315569

[Normal]
xilxBitgStart_Clk_DriveDone=xstvlg, SPARTAN2, Verilog.t_bitFile, 1046133500, True
p_impactConfigMode=xstvlg, SPARTAN2, Implementation.t_impactProgrammingTool, 1046315590, Slave Serial