__projnav.log

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ISE Auto-Make Log File
-----------------------

Updating: Configure Device (iMPACT)

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
ERROR:Portability:138 - Invalid file format, check the command argument file
   "__ngdbuild.rsp".
Usage: ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur
<rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off]
[-uc <ucf_file[.ucf]>] [-aul] [-i] [-modular initial|module|assemble] [-quiet]
[-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim
<pim_module_name>} <design_name> [<ngd_file[.ngd]>]

      -p  partname     Use specified part type to implement the design
      -sd source_dir   Add "source_dir" to the list of directories
                       to search when resolving netlist file references
      -l library       Add "library" to the list of source libraries
                       passed to the netlisters
      -ur rules_file   User rules file for netlist launcher
      -dd output_dir   Directory to place intermediate .ngo files
      -nt value        NGO file generation
                       Options:       "timestamp", "on", "off"
                       -nt timestamp: Regenerate NGO only when source
                                      netlist is newer than existing
                                      NGO file (default)
                       -nt on:        Always regenerate NGO file from
                                      source design netlists
                       -nt off:       Do not regenerate NGO files
                                      which already exist. Build NGD
                                      file from existing NGO files
      -uc ucf_file     Use specified "User Constraint File".
                       The file <design_name>.ucf is used by default
                       if it is found in the local directory.
      -r               Ignore location constraints
      -aul             Allow unmatched LOC constraints
      -a               Infer pad components from ports in top-level EDIF
                       netlist (if any)
      -i               Ignore usage of default ucf file, if present
      -u               Allow unexpanded blocks in output NGD design.
                       During partial design assembly flow, it gets used
                       along with -modular assemble switch to consider
                       unexpanded blocks as unimplemented modules.
      -modular initial|module|assemble
                       Modular design flows:
         -modular initial
                       Modular design in initial budgeting mode
         -modular module -active <active_module_name>
                       Modular design in active module mode
            -active <active_module_name>
                       Specifies the name of active module.
         -modular assemble -pimpath <pimpath> -use_pim <pim_module_name>
                       Modular design in assembly mode
            -pimpath <pimpath>
                       Specifies directory contains PIMs.
            -use_pim <pim_module_name>
                       Specifies an instantiated module in a top level design.
                       -use_pim can be used multiple times to specify multiple 
                       instantiated modules.
                       if -use_pim is missing, all subdirectories located in 
                       <pimpath> directory, which contain a .ngo file with the 
                       same subdirectory name, will be considered as valid 
                       instantiated modules.
      -quiet           Only report Warning and Error messages
      -verbose         Reports all messages
NGDBUILD:  Translates and merges the various source files of a design into a
single "NGD" design database.
EXEWRAP detected a return code of '2' from program 'ngdbuild'

Done: failed with exit code: 0002.

ISE Auto-Make Log File
-----------------------

Starting: 'exewrap @__filesAllClean_exewrap.rsp'


Creating TCL Process
Cleaning Up Project
deleting file(s): __projnav.log
deleting file(s): __impact.rsp __clock_2prj_exewrap.rsp __ednTOngd_exewrap.rsp __ngdbuild.rsp _map.rsp _ngdTOnc1_exewrap.rsp _par.rsp _prepar.rsp _nc1TOncd_exewrap.rsp bitgen.rsp __filesAllClean_exewrap.rsp
deleting file(s): clock.ngc
deleting file(s): clock.prj
deleting file(s): clock.xst
deleting file(s): clock.syr
deleting file(s): clock._prj
Finished cleaning up project

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_clock.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/xilinx_webpack/data/simprim.lst
Scanning    d:/xilinx_webpack/verilog/src/iSE/unisim_comp.v
Scanning    clock.v
Writing clock.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Configure Device (iMPACT)

Starting: 'exewrap @__clock_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/xilinx_webpack/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr'


Starting: 'D:/xilinx_webpack/bin/nt/xst.exe -ifn clock.xst -ofn clock.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.11 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : clock.prj

---- Target Parameters
Target Device                      : xc2s100-pq208-6
Output File Name                   : clock
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No
Incremental Synthesis              : NO

=========================================================================

 
Compiling source file : clock.prj
Compiling included source file 'clock.v'
Module <clock> compiled.
Continuing compilation of source file 'clock.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'clock.prj'
No errors in compilation
Analysis of file <clock.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <clock>.
WARNING:Xst:854 - "clock.v", line 12: Ignored initial statement.
WARNING:Xst:905 - "clock.v", line 30: The signals <sec> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 36: The signals <min> are missing in the sensitivity list of always block.
WARNING:Xst:905 - "clock.v", line 46: The signals <count, sec> are missing in the sensitivity list of always block.
Module <clock> is correct for synthesis.

Synthesizing Unit <clock>.
    Related source file is clock.v.
WARNING:Xst:737 - Found 1-bit latch for signal <keyen_reg>.
    Found 16x8-bit ROM for internal node.
    Found 4-bit adder for signal <$n0000> created at line 85.
    Found 4-bit adder for signal <$n0001> created at line 89.
    Found 4-bit adder for signal <$n0002> created at line 93.
    Found 4-bit adder for signal <$n0003> created at line 97.
    Found 30-bit adder for signal <$old_count_1>.
    Found 30-bit register for signal <count>.
    Found 4-bit 4-to-1 multiplexer for signal <ledbuf>.
    Found 16-bit register for signal <min>.
    Found 1-bit register for signal <sec>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred  47 D-type flip-flop(s).
	inferred   1 Latch(s).
	inferred   5 Adder/Subtracter(s).
	inferred  12 Multiplexer(s).
Unit <clock> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  30-bit register                  : 1
  1-bit register                   : 17
# Latches                          : 1
  1-bit latch                      : 1
# Multiplexers                     : 2
  4-bit 4-to-1 multiplexer         : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  30-bit adder                     : 1

=========================================================================


Starting low level synthesis...
Optimizing unit <clock> ...

Building and optimizing final netlist ...

=========================================================================
Final Results
Top Level Output File Name         : clock