pci_target_unit.v

用verilog编写的pci——rtl级。

wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr3_in =   pciu_bar3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr4_in =   pciu_bar4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr5_in =   pciu_bar5_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask0_in =   pciu_am0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask1_in =   pciu_am1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask2_in =   pciu_am2_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask3_in =   pciu_am3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask4_in =   pciu_am4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask5_in =   pciu_am5_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr0_in =   pciu_ta0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr1_in =   pciu_ta1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr2_in =   pciu_ta2_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr3_in =   pciu_ta3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr4_in =   pciu_ta4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr5_in =   pciu_ta5_in ;
wire        pcit_if_addr_tran_en0_in                =   pciu_at_en_in[0] ;
wire        pcit_if_addr_tran_en1_in                =   pciu_at_en_in[1] ;
wire        pcit_if_addr_tran_en2_in                =   pciu_at_en_in[2] ;
wire        pcit_if_addr_tran_en3_in                =   pciu_at_en_in[3] ;
wire        pcit_if_addr_tran_en4_in                =   pciu_at_en_in[4] ;
wire        pcit_if_addr_tran_en5_in                =   pciu_at_en_in[5] ;

pci_target32_interface pci_target_if
(
    .clk_in                         (pci_clock_in),
    .reset_in                       (reset_in),
    .address_in                     (pcit_if_address_in),
    .addr_claim_out                 (pcit_if_addr_claim_out),
    .bc_in                          (pcit_if_bc_in),
    .bc0_in                         (pcit_if_bc0_in),
    .data_in                        (pcit_if_data_in),
    .data_out                       (pcit_if_data_out),
    .be_in                          (pcit_if_be_in),
    .next_be_in                     (pcit_if_next_be_in),
    .req_in                         (pcit_if_req_in),
    .rdy_in                         (pcit_if_rdy_in),
    .addr_phase_in                  (pcit_if_addr_phase_in),
    .bckp_devsel_in                 (pcit_if_bckp_devsel_in),
    .bckp_trdy_in                   (pcit_if_bckp_trdy_in),
    .bckp_stop_in                   (pcit_if_bckp_stop_in),
    .last_reg_in                    (pcit_if_last_reg_in),
    .frame_reg_in                   (pcit_if_frame_reg_in),
    .fetch_pcir_fifo_in             (pcit_if_fetch_pcir_fifo_in),
    .load_medium_reg_in             (pcit_if_load_medium_reg_in),
    .sel_fifo_mreg_in               (pcit_if_sel_fifo_mreg_in),
    .sel_conf_fifo_in               (pcit_if_sel_conf_fifo_in),
    .load_to_pciw_fifo_in           (pcit_if_load_to_pciw_fifo_in),
    .load_to_conf_in                (pcit_if_load_to_conf_in),
    .same_read_out                  (pcit_if_same_read_out),
    .norm_access_to_config_out      (pcit_if_norm_access_to_config_out),
    .read_completed_out             (pcit_if_read_completed_out),
    .read_processing_out            (pcit_if_read_processing_out),
    .target_abort_out               (pcit_if_target_abort_out),
    .disconect_wo_data_out          (pcit_if_disconect_wo_data_out),
    .disconect_w_data_out			(pcit_if_disconect_w_data_out),
    .pciw_fifo_full_out             (pcit_if_pciw_fifo_full_out),
    .pcir_fifo_data_err_out         (pcit_if_pcir_fifo_data_err_out),
    .wbw_fifo_empty_out             (pcit_if_wbw_fifo_empty_out),
    .wbu_del_read_comp_pending_out	(pcit_if_wbu_del_read_comp_pending_out),
    .req_out                        (pcit_if_req_out),
    .done_out                       (pcit_if_done_out),
    .in_progress_out                (pcit_if_in_progress_out),
    .req_req_pending_in             (pcit_if_req_req_pending_in),
    .req_comp_pending_in            (pcit_if_req_comp_pending_in),
    .addr_out                       (pcit_if_addr_out),
    .be_out                         (pcit_if_be_out),
    .we_out                         (pcit_if_we_out),
    .bc_out                         (pcit_if_bc_out),
    .burst_ok_out                   (pcit_if_burst_ok_out),
    .strd_addr_in                   (pcit_if_strd_addr_in),
    .strd_bc_in                     (pcit_if_strd_bc_in),
    .status_in                      (pcit_if_status_in),
    .comp_flush_in                  (pcit_if_comp_flush_in),
    .pcir_fifo_renable_out          (pcit_if_pcir_fifo_renable_out),
    .pcir_fifo_data_in              (pcit_if_pcir_fifo_data_in),
    .pcir_fifo_be_in                (pcit_if_pcir_fifo_be_in),
    .pcir_fifo_control_in           (pcit_if_pcir_fifo_control_in),
    .pcir_fifo_flush_out            (pcit_if_pcir_fifo_flush_out),
    .pcir_fifo_almost_empty_in      (pcit_if_pcir_fifo_almost_empty_in),
    .pcir_fifo_empty_in             (pcit_if_pcir_fifo_empty_in),
    .pciw_fifo_wenable_out          (pcit_if_pciw_fifo_wenable_out),
    .pciw_fifo_addr_data_out        (pcit_if_pciw_fifo_addr_data_out),
    .pciw_fifo_cbe_out              (pcit_if_pciw_fifo_cbe_out),
    .pciw_fifo_control_out          (pcit_if_pciw_fifo_control_out),
    .pciw_fifo_three_left_in        (pcit_if_pciw_fifo_three_left_in),
    .pciw_fifo_two_left_in          (pcit_if_pciw_fifo_two_left_in),
    .pciw_fifo_almost_full_in       (pcit_if_pciw_fifo_almost_full_in),
    .pciw_fifo_full_in              (pcit_if_pciw_fifo_full_in),
    .wbw_fifo_empty_in              (pcit_if_wbw_fifo_empty_in),
    .wbu_del_read_comp_pending_in	(pcit_if_wbu_del_read_comp_pending_in),
    .conf_addr_out                  (pcit_if_conf_addr_out),
    .conf_data_out                  (pcit_if_conf_data_out),
    .conf_data_in                   (pcit_if_conf_data_in),
    .conf_be_out                    (pcit_if_conf_be_out),
    .conf_we_out                    (pcit_if_conf_we_out),
    .conf_re_out                    (pcit_if_conf_re_out),
    .mem_enable_in                  (pcit_if_mem_enable_in),
    .io_enable_in                   (pcit_if_io_enable_in),
    .mem_io_addr_space0_in          (pcit_if_mem_io_addr_space0_in),
    .mem_io_addr_space1_in          (pcit_if_mem_io_addr_space1_in),
    .mem_io_addr_space2_in          (pcit_if_mem_io_addr_space2_in),
    .mem_io_addr_space3_in          (pcit_if_mem_io_addr_space3_in),
    .mem_io_addr_space4_in          (pcit_if_mem_io_addr_space4_in),
    .mem_io_addr_space5_in          (pcit_if_mem_io_addr_space5_in),
    .pre_fetch_en0_in               (pcit_if_pre_fetch_en0_in),
    .pre_fetch_en1_in               (pcit_if_pre_fetch_en1_in),
    .pre_fetch_en2_in               (pcit_if_pre_fetch_en2_in),
    .pre_fetch_en3_in               (pcit_if_pre_fetch_en3_in),
    .pre_fetch_en4_in               (pcit_if_pre_fetch_en4_in),
    .pre_fetch_en5_in               (pcit_if_pre_fetch_en5_in),
    .pci_base_addr0_in              (pcit_if_pci_base_addr0_in),
    .pci_base_addr1_in              (pcit_if_pci_base_addr1_in),
    .pci_base_addr2_in              (pcit_if_pci_base_addr2_in),
    .pci_base_addr3_in              (pcit_if_pci_base_addr3_in),
    .pci_base_addr4_in              (pcit_if_pci_base_addr4_in),
    .pci_base_addr5_in              (pcit_if_pci_base_addr5_in),
    .pci_addr_mask0_in              (pcit_if_pci_addr_mask0_in),
    .pci_addr_mask1_in              (pcit_if_pci_addr_mask1_in),
    .pci_addr_mask2_in              (pcit_if_pci_addr_mask2_in),
    .pci_addr_mask3_in              (pcit_if_pci_addr_mask3_in),
    .pci_addr_mask4_in              (pcit_if_pci_addr_mask4_in),
    .pci_addr_mask5_in              (pcit_if_pci_addr_mask5_in),
    .pci_tran_addr0_in              (pcit_if_pci_tran_addr0_in),
    .pci_tran_addr1_in              (pcit_if_pci_tran_addr1_in),
    .pci_tran_addr2_in              (pcit_if_pci_tran_addr2_in),
    .pci_tran_addr3_in              (pcit_if_pci_tran_addr3_in),
    .pci_tran_addr4_in              (pcit_if_pci_tran_addr4_in),
    .pci_tran_addr5_in              (pcit_if_pci_tran_addr5_in),
    .addr_tran_en0_in               (pcit_if_addr_tran_en0_in),
    .addr_tran_en1_in               (pcit_if_addr_tran_en1_in),
    .addr_tran_en2_in               (pcit_if_addr_tran_en2_in),
    .addr_tran_en3_in               (pcit_if_addr_tran_en3_in),
    .addr_tran_en4_in               (pcit_if_addr_tran_en4_in),
    .addr_tran_en5_in               (pcit_if_addr_tran_en5_in)
) ;

// pci target state machine inputs
wire        pcit_sm_frame_in                    =   pciu_pciif_frame_in ;
wire        pcit_sm_irdy_in                     =   pciu_pciif_irdy_in ;
wire        pcit_sm_idsel_in                    =   pciu_pciif_idsel_in ;
wire        pcit_sm_frame_reg_in                =   pciu_pciif_frame_reg_in ;
wire        pcit_sm_irdy_reg_in                 =   pciu_pciif_irdy_reg_in ;
wire        pcit_sm_idsel_reg_in                =   pciu_pciif_idsel_reg_in ;
wire [31:0] pcit_sm_ad_reg_in                   =   pciu_pciif_ad_reg_in ;
wire  [3:0] pcit_sm_cbe_reg_in                  =   pciu_pciif_cbe_reg_in ;
wire  [3:0] pcit_sm_cbe_in                      =   pciu_pciif_cbe_in ;
wire        pcit_sm_bckp_trdy_en_in             =   pciu_pciif_bckp_trdy_en_in ;
wire        pcit_sm_bckp_devsel_in              =   pciu_pciif_bckp_devsel_in ;
wire        pcit_sm_bckp_trdy_in                =   pciu_pciif_bckp_trdy_in ;
wire        pcit_sm_bckp_stop_in                =   pciu_pciif_bckp_stop_in ;
wire        pcit_sm_addr_claim_in               =   pcit_if_addr_claim_out ;
wire [31:0] pcit_sm_data_in                     =   pcit_if_data_out ;
wire        pcit_sm_same_read_in                =   pcit_if_same_read_out ;
wire        pcit_sm_norm_access_to_config_in    =   pcit_if_norm_access_to_config_out ;
wire        pcit_sm_read_completed_in           =   pcit_if_read_completed_out ;
wire        pcit_sm_read_processing_in          =   pcit_if_read_processing_out ;
wire        pcit_sm_target_abort_in             =   pcit_if_target_abort_out ;
wire        pcit_sm_disconect_wo_data_in        =   pcit_if_disconect_wo_data_out ;
wire		pcit_sm_disconect_w_data_in			=	pcit_if_disconect_w_data_out ;
wire        pcit_sm_pciw_fifo_full_in           =   pcit_if_pciw_fifo_full_out ;
wire        pcit_sm_pcir_fifo_data_err_in       =   pcit_if_pcir_fifo_data_err_out ;
wire        pcit_sm_wbw_fifo_empty_in           =   pcit_if_wbw_fifo_empty_out ;
wire		pcit_sm_wbu_del_read_comp_pending_in	=	pcit_if_wbu_del_read_comp_pending_out ;
wire        pcit_sm_wbu_frame_en_in             =   pciu_wbu_frame_en_in ;
wire        pcit_sm_trdy_reg_in                 =   pciu_pciif_trdy_reg_in ;
wire        pcit_sm_stop_reg_in                 =   pciu_pciif_stop_reg_in ;


pci_target32_sm pci_target_sm
(
    .clk_in                             (pci_clock_in),
    .reset_in                           (reset_in),
    .pci_frame_in                       (pcit_sm_frame_in),
    .pci_irdy_in                        (pcit_sm_irdy_in),
    .pci_idsel_in                       (pcit_sm_idsel_in),
    .pci_frame_reg_in                   (pcit_sm_frame_reg_in),
    .pci_irdy_reg_in                    (pcit_sm_irdy_reg_in),
    .pci_idsel_reg_in                   (pcit_sm_idsel_reg_in),
    .pci_trdy_out                       (pcit_sm_trdy_out),
    .pci_stop_out                       (pcit_sm_stop_out),
    .pci_devsel_out                     (pcit_sm_devsel_out),
    .pci_trdy_en_out                    (pcit_sm_trdy_en_out),
    .pci_stop_en_out                    (pcit_sm_stop_en_out),
    .pci_devsel_en_out                  (pcit_sm_devsel_en_out),
    .ad_load_out                        (pcit_sm_ad_load_out),
    .ad_load_on_transfer_out            (pcit_sm_ad_load_on_transfer_out),
    .pci_ad_reg_in                      (pcit_sm_ad_reg_in),
    .pci_ad_out                         (pcit_sm_ad_out),
    .pci_ad_en_out                      (pcit_sm_ad_en_out),
    .pci_cbe_reg_in                     (pcit_sm_cbe_reg_in),
    .pci_cbe_in                         (pcit_sm_cbe_in),
    .bckp_trdy_en_in                    (pcit_sm_bckp_trdy_en_in),
    .bckp_devsel_in                     (pcit_sm_bckp_devsel_in),
    .bckp_trdy_in                       (pcit_sm_bckp_trdy_in),
    .bckp_stop_in                       (pcit_sm_bckp_stop_in),
    .pci_trdy_reg_in                    (pcit_sm_trdy_reg_in),
    .pci_stop_reg_in                    (pcit_sm_stop_reg_in),
    .address_out                        (pcit_sm_address_out),
    .addr_claim_in                      (pcit_sm_addr_claim_in),
    .bc_out                             (pcit_sm_bc_out),
    .bc0_out                            (pcit_sm_bc0_out),
    .data_out                           (pcit_sm_data_out),
    .data_in                            (pcit_sm_data_in),
    .be_out                             (pcit_sm_be_out),
    .next_be_out                        (pcit_sm_next_be_out),
    .req_out                            (pcit_sm_req_out),
    .rdy_out                            (pcit_sm_rdy_out),
    .addr_phase_out                     (pcit_sm_addr_phase_out),
    .bckp_devsel_out					(pcit_sm_bckp_devsel_out),
    .bckp_trdy_out                      (pcit_sm_bckp_trdy_out),
    .bckp_stop_out						(pcit_sm_bckp_stop_out),
    .last_reg_out                       (pcit_sm_last_reg_out),
    .frame_reg_out                      (pcit_sm_frame_reg_out),
    .fetch_pcir_fifo_out                (pcit_sm_fetch_pcir_fifo_out),
    .load_medium_reg_out                (pcit_sm_load_medium_reg_out),
    .sel_fifo_mreg_out                  (pcit_sm_sel_fifo_mreg_out),
    .sel_conf_fifo_out                  (pcit_sm_sel_conf_fifo_out),
    .load_to_pciw_fifo_out              (pcit_sm_load_to_pciw_fifo_out),
    .load_to_conf_out                   (pcit_sm_load_to_conf_out),
    .same_read_in                       (pcit_sm_same_read_in),
    .norm_access_to_config_in           (pcit_sm_norm_access_to_config_in),
    .read_completed_in                  (pcit_sm_read_completed_in),
    .read_processing_in                 (pcit_sm_read_processing_in),
    .target_abort_in                    (pcit_sm_target_abort_in),
    .disconect_wo_data_in               (pcit_sm_disconect_wo_data_in),
    .disconect_w_data_in				(pcit_sm_disconect_w_data_in),
    .target_abort_set_out               (pcit_sm_target_abort_set_out),
    .pciw_fifo_full_in                  (pcit_sm_pciw_fifo_full_in),
    .pcir_fifo_data_err_in              (pcit_sm_pcir_fifo_data_err_in),
    .wbw_fifo_empty_in                  (pcit_sm_wbw_fifo_empty_in),
    .wbu_del_read_comp_pending_in		(pcit_sm_wbu_del_read_comp_pending_in),
    .wbu_frame_en_in                    (pcit_sm_wbu_frame_en_in)
) ;

endmodule