pci_target_unit.v

用verilog编写的pci——rtl级。

wire [31:0] del_sync_addr_out ;
wire [3:0]  del_sync_be_out ;
wire        del_sync_we_out ;
wire        del_sync_comp_req_pending_out ;
wire        del_sync_comp_comp_pending_out ;
wire        del_sync_req_req_pending_out ;
wire        del_sync_req_comp_pending_out ;
wire [3:0]  del_sync_bc_out ;
wire        del_sync_status_out ;
wire        del_sync_comp_flush_out ;
wire        del_sync_burst_out ;

assign  pciu_pci_drcomp_pending_out = del_sync_comp_comp_pending_out ;

// WISHBONE master interface inputs
wire        wbm_sm_pci_tar_read_request             =   del_sync_comp_req_pending_out ;
wire [31:0] wbm_sm_pci_tar_address                  =   del_sync_addr_out ;
wire  [3:0] wbm_sm_pci_tar_cmd                      =   del_sync_bc_out ;
wire  [3:0] wbm_sm_pci_tar_be                       =   del_sync_be_out ;
wire        wbm_sm_pci_tar_burst_ok                 =   del_sync_burst_out ;
wire  [7:0] wbm_sm_pci_cache_line_size              =   pciu_cache_line_size_in ;
wire        wbm_sm_cache_lsize_not_zero_in          =   pciu_cache_lsize_not_zero_in ;
wire [31:0] wbm_sm_pciw_fifo_addr_data_in           =   fifos_pciw_addr_data_out ;
wire  [3:0] wbm_sm_pciw_fifo_cbe_in                 =   fifos_pciw_cbe_out ;
wire  [3:0] wbm_sm_pciw_fifo_control_in             =   fifos_pciw_control_out ;
wire        wbm_sm_pciw_fifo_almost_empty_in        =   fifos_pciw_almost_empty_out ;
wire        wbm_sm_pciw_fifo_empty_in               =   fifos_pciw_empty_out ;
wire        wbm_sm_pciw_fifo_transaction_ready_in   =   fifos_pciw_transaction_ready_out ;
wire [31:0] wbm_sm_mdata_in                         =   pciu_wbm_dat_i ;
wire        wbm_sm_ack_in                           =   pciu_wbm_ack_i ;
wire        wbm_sm_rty_in                           =   pciu_wbm_rty_i ;
wire        wbm_sm_err_in                           =   pciu_wbm_err_i ;

// WISHBONE master interface instantiation
pci_wb_master wishbone_master
(
    .wb_clock_in                    (wb_clock_in),
    .reset_in                       (reset_in),
    .pci_tar_read_request           (wbm_sm_pci_tar_read_request),  //in
    .pci_tar_address                (wbm_sm_pci_tar_address),       //in
    .pci_tar_cmd                    (wbm_sm_pci_tar_cmd),           //in
    .pci_tar_be                     (wbm_sm_pci_tar_be),            //in
    .pci_tar_burst_ok				(wbm_sm_pci_tar_burst_ok),		//in
    .pci_cache_line_size            (wbm_sm_pci_cache_line_size),   //in
    .cache_lsize_not_zero           (wbm_sm_cache_lsize_not_zero_in),
    .wb_read_done_out               (wbm_sm_wb_read_done),          //out
    .w_attempt						(wbm_sm_write_attempt),			//out
    .pcir_fifo_wenable_out          (wbm_sm_pcir_fifo_wenable_out),
    .pcir_fifo_data_out             (wbm_sm_pcir_fifo_data_out),
    .pcir_fifo_be_out               (wbm_sm_pcir_fifo_be_out),
    .pcir_fifo_control_out          (wbm_sm_pcir_fifo_control_out),
    .pciw_fifo_renable_out          (wbm_sm_pciw_fifo_renable_out),
    .pciw_fifo_addr_data_in         (wbm_sm_pciw_fifo_addr_data_in),
    .pciw_fifo_cbe_in               (wbm_sm_pciw_fifo_cbe_in),
    .pciw_fifo_control_in           (wbm_sm_pciw_fifo_control_in),
    .pciw_fifo_almost_empty_in      (wbm_sm_pciw_fifo_almost_empty_in),
    .pciw_fifo_empty_in             (wbm_sm_pciw_fifo_empty_in),
    .pciw_fifo_transaction_ready_in (wbm_sm_pciw_fifo_transaction_ready_in),
    .pci_error_sig_out              (wbm_sm_pci_error_sig_out),
    .pci_error_bc                   (wbm_sm_pci_error_bc),
    .write_rty_cnt_exp_out          (wbm_sm_write_rty_cnt_exp_out),
    .error_source_out               (wbm_sm_error_source_out),
    .read_rty_cnt_exp_out           (wbm_sm_read_rty_cnt_exp_out),
    .wb_cyc_o                      (wbm_sm_cyc_out),
    .wb_stb_o                      (wbm_sm_stb_out),
    .wb_we_o                       (wbm_sm_we_out),
    .wb_cti_o                      (wbm_sm_cti_out),
    .wb_bte_o                      (wbm_sm_bte_out),
    .wb_sel_o                      (wbm_sm_sel_out),
    .wb_adr_o                      (wbm_sm_adr_out),
    .wb_dat_i                      (wbm_sm_mdata_in),
    .wb_dat_o                      (wbm_sm_mdata_out),
    .wb_ack_i                      (wbm_sm_ack_in),
    .wb_rty_i                      (wbm_sm_rty_in),
    .wb_err_i                      (wbm_sm_err_in)
);

// pciw_pcir_fifos inputs
// PCIW_FIFO inputs
wire        fifos_pciw_wenable_in       =   pcit_if_pciw_fifo_wenable_out ;
wire [31:0] fifos_pciw_addr_data_in     =   pcit_if_pciw_fifo_addr_data_out ;
wire [3:0]  fifos_pciw_cbe_in           =   pcit_if_pciw_fifo_cbe_out ;
wire [3:0]  fifos_pciw_control_in       =   pcit_if_pciw_fifo_control_out ;
wire        fifos_pciw_renable_in       =   wbm_sm_pciw_fifo_renable_out ;
//wire        fifos_pciw_flush_in         =   1'b0 ;    // flush not used for write fifo

// PCIR_FIFO inputs
wire        fifos_pcir_wenable_in       =   wbm_sm_pcir_fifo_wenable_out ;
wire [31:0] fifos_pcir_data_in          =   wbm_sm_pcir_fifo_data_out ;
wire [3:0]  fifos_pcir_be_in            =   wbm_sm_pcir_fifo_be_out ;
wire [3:0]  fifos_pcir_control_in       =   wbm_sm_pcir_fifo_control_out ;
wire        fifos_pcir_renable_in       =   pcit_if_pcir_fifo_renable_out ;
wire        fifos_pcir_flush_in         =   pcit_if_pcir_fifo_flush_out ;

// PCIW_FIFO and PCIR_FIFO instantiation
pci_pciw_pcir_fifos fifos
(
    .wb_clock_in                (wb_clock_in),
    .pci_clock_in               (pci_clock_in),
    .reset_in                   (reset_in),
    .pciw_wenable_in            (fifos_pciw_wenable_in),      //for PCI Target !!!
    .pciw_addr_data_in          (fifos_pciw_addr_data_in),    //for PCI Target !!!
    .pciw_cbe_in                (fifos_pciw_cbe_in),          //for PCI Target !!!
    .pciw_control_in            (fifos_pciw_control_in),      //for PCI Target !!!
    .pciw_renable_in            (fifos_pciw_renable_in),
    .pciw_addr_data_out         (fifos_pciw_addr_data_out),
    .pciw_cbe_out               (fifos_pciw_cbe_out),
    .pciw_control_out           (fifos_pciw_control_out),
//    .pciw_flush_in              (fifos_pciw_flush_in),      // flush not used for write fifo
    .pciw_three_left_out        (fifos_pciw_three_left_out),  //for PCI Target !!!
    .pciw_two_left_out          (fifos_pciw_two_left_out),    //for PCI Target !!!
    .pciw_almost_full_out       (fifos_pciw_almost_full_out), //for PCI Target !!!
    .pciw_full_out              (fifos_pciw_full_out),        //for PCI Target !!!
    .pciw_almost_empty_out      (fifos_pciw_almost_empty_out),
    .pciw_empty_out             (fifos_pciw_empty_out),
    .pciw_transaction_ready_out (fifos_pciw_transaction_ready_out),
    .pcir_wenable_in            (fifos_pcir_wenable_in),
    .pcir_data_in               (fifos_pcir_data_in),
    .pcir_be_in                 (fifos_pcir_be_in),
    .pcir_control_in            (fifos_pcir_control_in),
    .pcir_renable_in            (fifos_pcir_renable_in),      //for PCI Target !!!
    .pcir_data_out              (fifos_pcir_data_out),        //for PCI Target !!!
    .pcir_be_out                (fifos_pcir_be_out),          //for PCI Target !!!
    .pcir_control_out           (fifos_pcir_control_out),     //for PCI Target !!!
    .pcir_flush_in              (fifos_pcir_flush_in),        //for PCI Target !!!
    .pcir_full_out              (),
    .pcir_almost_empty_out      (fifos_pcir_almost_empty_out), //for PCI Target !!!
    .pcir_empty_out             (fifos_pcir_empty_out),        //for PCI Target !!!
    .pcir_transaction_ready_out ()

`ifdef PCI_BIST
    ,
    .mbist_si_i       (mbist_si_i),
    .mbist_so_o       (mbist_so_o),
    .mbist_ctrl_i       (mbist_ctrl_i)
`endif
) ;

// delayed transaction logic inputs
wire        del_sync_req_in             =   pcit_if_req_out ;
wire        del_sync_comp_in            =   wbm_sm_wb_read_done ;
wire        del_sync_done_in            =   pcit_if_done_out ;
wire        del_sync_in_progress_in     =   pcit_if_in_progress_out ;
wire [31:0] del_sync_addr_in            =   pcit_if_addr_out ;
wire  [3:0] del_sync_be_in              =   pcit_if_be_out ;
wire        del_sync_we_in              =   pcit_if_we_out ;
wire  [3:0] del_sync_bc_in              =   pcit_if_bc_out ;
wire        del_sync_status_in          =   1'b0 ;
wire        del_sync_burst_in           =   pcit_if_burst_ok_out ;
wire        del_sync_retry_expired_in   =   wbm_sm_read_rty_cnt_exp_out ;

// delayed transaction logic instantiation
pci_delayed_sync del_sync
(
    .reset_in               (reset_in),
    .req_clk_in             (pci_clock_in),
    .comp_clk_in            (wb_clock_in),
    .req_in                 (del_sync_req_in),
    .comp_in                (del_sync_comp_in),
    .done_in                (del_sync_done_in),
    .in_progress_in         (del_sync_in_progress_in),
    .comp_req_pending_out   (del_sync_comp_req_pending_out),
    .comp_comp_pending_out  (del_sync_comp_comp_pending_out),
    .req_req_pending_out    (del_sync_req_req_pending_out),
    .req_comp_pending_out   (del_sync_req_comp_pending_out),
    .addr_in                (del_sync_addr_in),
    .be_in                  (del_sync_be_in),
    .addr_out               (del_sync_addr_out),
    .be_out                 (del_sync_be_out),
    .we_in                  (del_sync_we_in),
    .we_out                 (del_sync_we_out),
    .bc_in                  (del_sync_bc_in),
    .bc_out                 (del_sync_bc_out),
    .status_in              (del_sync_status_in),
    .status_out             (del_sync_status_out),
    .comp_flush_out         (del_sync_comp_flush_out),
    .burst_in               (del_sync_burst_in),
    .burst_out              (del_sync_burst_out),
    .retry_expired_in       (del_sync_retry_expired_in)
);

// pci target interface inputs
wire [31:0] pcit_if_address_in                      =   pcit_sm_address_out ;
wire  [3:0] pcit_if_bc_in                           =   pcit_sm_bc_out ;
wire        pcit_if_bc0_in                          =   pcit_sm_bc0_out ;
wire [31:0] pcit_if_data_in                         =   pcit_sm_data_out ;
wire  [3:0] pcit_if_be_in                           =   pcit_sm_be_out ;
wire  [3:0] pcit_if_next_be_in                      =   pcit_sm_next_be_out ;
wire        pcit_if_req_in                          =   pcit_sm_req_out ;
wire        pcit_if_rdy_in                          =   pcit_sm_rdy_out ;
wire        pcit_if_addr_phase_in                   =   pcit_sm_addr_phase_out ;
wire		pcit_if_bckp_devsel_in					=	pcit_sm_bckp_devsel_out ;
wire        pcit_if_bckp_trdy_in                    =   pcit_sm_bckp_trdy_out ;
wire		pcit_if_bckp_stop_in					=	pcit_sm_bckp_stop_out ;
wire        pcit_if_last_reg_in                     =   pcit_sm_last_reg_out ;
wire        pcit_if_frame_reg_in                    =   pcit_sm_frame_reg_out ;
wire        pcit_if_fetch_pcir_fifo_in              =   pcit_sm_fetch_pcir_fifo_out ;
wire        pcit_if_load_medium_reg_in              =   pcit_sm_load_medium_reg_out ;
wire        pcit_if_sel_fifo_mreg_in                =   pcit_sm_sel_fifo_mreg_out ;
wire        pcit_if_sel_conf_fifo_in                =   pcit_sm_sel_conf_fifo_out ;
wire        pcit_if_load_to_pciw_fifo_in            =   pcit_sm_load_to_pciw_fifo_out ;
wire        pcit_if_load_to_conf_in                 =   pcit_sm_load_to_conf_out ;
wire        pcit_if_req_req_pending_in              =   del_sync_req_req_pending_out ;
wire        pcit_if_req_comp_pending_in             =   del_sync_req_comp_pending_out ;
wire        pcit_if_status_in                       =   del_sync_status_out ;
wire [31:0] pcit_if_strd_addr_in                    =   del_sync_addr_out ;
wire  [3:0] pcit_if_strd_bc_in                      =   del_sync_bc_out ;
wire        pcit_if_comp_flush_in                   =   del_sync_comp_flush_out ;
wire [31:0] pcit_if_pcir_fifo_data_in               =   fifos_pcir_data_out ;
wire  [3:0] pcit_if_pcir_fifo_be_in                 =   fifos_pcir_be_out ;
wire  [3:0] pcit_if_pcir_fifo_control_in            =   fifos_pcir_control_out ;
wire        pcit_if_pcir_fifo_almost_empty_in       =   fifos_pcir_almost_empty_out ;
wire        pcit_if_pcir_fifo_empty_in              =   fifos_pcir_empty_out ;
wire        pcit_if_pciw_fifo_three_left_in         =   fifos_pciw_three_left_out ;
wire        pcit_if_pciw_fifo_two_left_in           =   fifos_pciw_two_left_out ;
wire        pcit_if_pciw_fifo_almost_full_in        =   fifos_pciw_almost_full_out ;
wire        pcit_if_pciw_fifo_full_in               =   fifos_pciw_full_out ;
wire        pcit_if_wbw_fifo_empty_in               =   pciu_wbw_fifo_empty_in ;
wire		pcit_if_wbu_del_read_comp_pending_in	=	pciu_wbu_del_read_comp_pending_in ;
wire [31:0] pcit_if_conf_data_in                    =   pciu_conf_data_in ;
wire        pcit_if_mem_enable_in                   =   pciu_mem_enable_in ;
wire        pcit_if_io_enable_in                    =   pciu_io_enable_in ;
wire        pcit_if_mem_io_addr_space0_in           =   pciu_map_in[0] ;
wire        pcit_if_mem_io_addr_space1_in           =   pciu_map_in[1] ;
wire        pcit_if_mem_io_addr_space2_in           =   pciu_map_in[2] ;
wire        pcit_if_mem_io_addr_space3_in           =   pciu_map_in[3] ;
wire        pcit_if_mem_io_addr_space4_in           =   pciu_map_in[4] ;
wire        pcit_if_mem_io_addr_space5_in           =   pciu_map_in[5] ;
wire        pcit_if_pre_fetch_en0_in                =   pciu_pref_en_in[0] ;
wire        pcit_if_pre_fetch_en1_in                =   pciu_pref_en_in[1] ;
wire        pcit_if_pre_fetch_en2_in                =   pciu_pref_en_in[2] ;
wire        pcit_if_pre_fetch_en3_in                =   pciu_pref_en_in[3] ;
wire        pcit_if_pre_fetch_en4_in                =   pciu_pref_en_in[4] ;
wire        pcit_if_pre_fetch_en5_in                =   pciu_pref_en_in[5] ;
wire [(pci_ba0_width   - 1):0] pcit_if_pci_base_addr0_in =   pciu_bar0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr1_in =   pciu_bar1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr2_in =   pciu_bar2_in ;