pci_target_unit.v

用verilog编写的pci——rtl级。

input           pciu_wbu_frame_en_in ;

input           pciu_mem_enable_in ;
input           pciu_io_enable_in ;
input   [5:0]   pciu_map_in ;
input   [5:0]   pciu_pref_en_in ;
input   [31:0]  pciu_conf_data_in ;

input   [pci_ba0_width   - 1:0] pciu_bar0_in ;
input   [pci_ba1_5_width - 1:0] pciu_bar1_in ;
input   [pci_ba1_5_width - 1:0] pciu_bar2_in ;
input   [pci_ba1_5_width - 1:0] pciu_bar3_in ;
input   [pci_ba1_5_width - 1:0] pciu_bar4_in ;
input   [pci_ba1_5_width - 1:0] pciu_bar5_in ;
input   [pci_ba1_5_width - 1:0] pciu_am0_in ;
input   [pci_ba1_5_width - 1:0] pciu_am1_in ;
input   [pci_ba1_5_width - 1:0] pciu_am2_in ;
input   [pci_ba1_5_width - 1:0] pciu_am3_in ;
input   [pci_ba1_5_width - 1:0] pciu_am4_in ;
input   [pci_ba1_5_width - 1:0] pciu_am5_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta0_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta1_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta2_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta3_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta4_in ;
input   [pci_ba1_5_width - 1:0] pciu_ta5_in ;
input   [5:0]                   pciu_at_en_in ;

input   [7:0]   pciu_cache_line_size_in ;
input           pciu_cache_lsize_not_zero_in ;

input           pciu_pciif_frame_in ;
input           pciu_pciif_irdy_in ;
input           pciu_pciif_idsel_in ;
input           pciu_pciif_frame_reg_in ;
input           pciu_pciif_irdy_reg_in ;
input           pciu_pciif_idsel_reg_in ;
input  [31:0]   pciu_pciif_ad_reg_in ;
input   [3:0]   pciu_pciif_cbe_reg_in ;
input   [3:0]   pciu_pciif_cbe_in;
input           pciu_pciif_bckp_trdy_en_in ;
input           pciu_pciif_bckp_devsel_in ;
input           pciu_pciif_bckp_trdy_in ;
input           pciu_pciif_bckp_stop_in ;
input           pciu_pciif_trdy_reg_in ;
input           pciu_pciif_stop_reg_in ;


output          pciu_pciif_trdy_out ;
output          pciu_pciif_stop_out ;
output          pciu_pciif_devsel_out ;
output          pciu_pciif_trdy_en_out ;
output          pciu_pciif_stop_en_out ;
output          pciu_pciif_devsel_en_out ;
output          pciu_ad_load_out ;
output          pciu_ad_load_on_transfer_out ;
output [31:0]   pciu_pciif_ad_out ;
output          pciu_pciif_ad_en_out ;
output          pciu_pciif_tabort_set_out ;

output  [31:0]  pciu_err_addr_out ;
output  [3:0]   pciu_err_bc_out ;
output  [31:0]  pciu_err_data_out ;
output  [3:0]   pciu_err_be_out ;
output          pciu_err_signal_out ;
output          pciu_err_source_out ;
output          pciu_err_rty_exp_out ;

output  [11:0]  pciu_conf_offset_out ;
output          pciu_conf_renable_out ;
output          pciu_conf_wenable_out ;
output  [3:0]   pciu_conf_be_out ;
output  [31:0]  pciu_conf_data_out ;

output          pciu_pci_drcomp_pending_out ;
output          pciu_pciw_fifo_empty_out ;

`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input   mbist_si_i;       // bist scan serial in
output  mbist_so_o;       // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif


// pci target state machine and interface outputs
wire        pcit_sm_trdy_out ;
wire        pcit_sm_stop_out ;
wire        pcit_sm_devsel_out ;
wire        pcit_sm_trdy_en_out ;
wire        pcit_sm_stop_en_out ;
wire        pcit_sm_devsel_en_out ;
wire        pcit_sm_ad_load_out ;
wire        pcit_sm_ad_load_on_transfer_out ;
wire [31:0] pcit_sm_ad_out ;
wire        pcit_sm_ad_en_out ;
wire [31:0] pcit_sm_address_out ;
wire  [3:0] pcit_sm_bc_out ;
wire        pcit_sm_bc0_out ;
wire [31:0] pcit_sm_data_out ;
wire  [3:0] pcit_sm_be_out ;
wire  [3:0] pcit_sm_next_be_out ;
wire        pcit_sm_req_out ;
wire        pcit_sm_rdy_out ;
wire        pcit_sm_addr_phase_out ;
wire		pcit_sm_bckp_devsel_out ;
wire        pcit_sm_bckp_trdy_out ;
wire		pcit_sm_bckp_stop_out ;
wire        pcit_sm_last_reg_out ;
wire        pcit_sm_frame_reg_out ;
wire        pcit_sm_fetch_pcir_fifo_out ;
wire        pcit_sm_load_medium_reg_out ;
wire        pcit_sm_sel_fifo_mreg_out ;
wire        pcit_sm_sel_conf_fifo_out ;
wire        pcit_sm_load_to_pciw_fifo_out ;
wire        pcit_sm_load_to_conf_out ;

wire        pcit_sm_target_abort_set_out ; // to conf space

assign  pciu_pciif_trdy_out             =   pcit_sm_trdy_out ;
assign  pciu_pciif_stop_out             =   pcit_sm_stop_out ;
assign  pciu_pciif_devsel_out           =   pcit_sm_devsel_out ;
assign  pciu_pciif_trdy_en_out          =   pcit_sm_trdy_en_out ;
assign  pciu_pciif_stop_en_out          =   pcit_sm_stop_en_out ;
assign  pciu_pciif_devsel_en_out        =   pcit_sm_devsel_en_out ;
assign  pciu_ad_load_out                =   pcit_sm_ad_load_out ;
assign  pciu_ad_load_on_transfer_out    =   pcit_sm_ad_load_on_transfer_out ;
assign  pciu_pciif_ad_out               =   pcit_sm_ad_out ;
assign  pciu_pciif_ad_en_out            =   pcit_sm_ad_en_out ;
assign  pciu_pciif_tabort_set_out       =   pcit_sm_target_abort_set_out ;

wire        pcit_if_addr_claim_out ;
wire [31:0] pcit_if_data_out ;
wire        pcit_if_same_read_out ;
wire        pcit_if_norm_access_to_config_out ;
wire        pcit_if_read_completed_out ;
wire        pcit_if_read_processing_out ;
wire        pcit_if_target_abort_out ;
wire        pcit_if_disconect_wo_data_out ;
wire		pcit_if_disconect_w_data_out ;
wire        pcit_if_pciw_fifo_full_out ;
wire        pcit_if_pcir_fifo_data_err_out ;
wire        pcit_if_wbw_fifo_empty_out ;
wire		pcit_if_wbu_del_read_comp_pending_out ;
wire        pcit_if_req_out ;
wire        pcit_if_done_out ;
wire        pcit_if_in_progress_out ;
wire [31:0] pcit_if_addr_out ;
wire  [3:0] pcit_if_be_out ;
wire        pcit_if_we_out ;
wire  [3:0] pcit_if_bc_out ;
wire        pcit_if_burst_ok_out ;
wire        pcit_if_pcir_fifo_renable_out ;
wire        pcit_if_pcir_fifo_flush_out ;
wire        pcit_if_pciw_fifo_wenable_out ;
wire [31:0] pcit_if_pciw_fifo_addr_data_out ;
wire  [3:0] pcit_if_pciw_fifo_cbe_out ;
wire  [3:0] pcit_if_pciw_fifo_control_out ;
wire [11:0] pcit_if_conf_addr_out ;
wire [31:0] pcit_if_conf_data_out ;
wire  [3:0] pcit_if_conf_be_out ;
wire        pcit_if_conf_we_out ;
wire        pcit_if_conf_re_out ;

// pci target state machine outputs
// pci interface signals
assign  pciu_conf_offset_out    =   pcit_if_conf_addr_out ;
assign  pciu_conf_renable_out   =   pcit_if_conf_re_out ;
assign  pciu_conf_wenable_out   =   pcit_if_conf_we_out ;
assign  pciu_conf_be_out        =   pcit_if_conf_be_out ;
assign  pciu_conf_data_out      =   pcit_if_conf_data_out ;

// wishbone master state machine outputs
wire        wbm_sm_wb_read_done ;
wire		wbm_sm_write_attempt ;
wire        wbm_sm_pcir_fifo_wenable_out ;
wire [31:0] wbm_sm_pcir_fifo_data_out ;
wire  [3:0] wbm_sm_pcir_fifo_be_out ;
wire  [3:0] wbm_sm_pcir_fifo_control_out ;
wire        wbm_sm_pciw_fifo_renable_out ;
wire        wbm_sm_pci_error_sig_out ;
wire  [3:0] wbm_sm_pci_error_bc ;
wire        wbm_sm_write_rty_cnt_exp_out ;
wire        wbm_sm_error_source_out ;
wire        wbm_sm_read_rty_cnt_exp_out ;
wire        wbm_sm_cyc_out ;
wire        wbm_sm_stb_out ;
wire        wbm_sm_we_out ;
wire  [2:0] wbm_sm_cti_out ;
wire  [1:0] wbm_sm_bte_out ;
wire  [3:0] wbm_sm_sel_out ;
wire [31:0] wbm_sm_adr_out ;
wire [31:0] wbm_sm_mdata_out ;

assign  pciu_err_addr_out       =   wbm_sm_adr_out ;
assign  pciu_err_bc_out         =   wbm_sm_pci_error_bc ;
assign  pciu_err_data_out       =   wbm_sm_mdata_out ;
assign  pciu_err_be_out         =   ~wbm_sm_sel_out ;
assign  pciu_err_signal_out     =   wbm_sm_pci_error_sig_out ;
assign  pciu_err_source_out     =   wbm_sm_error_source_out ;
assign  pciu_err_rty_exp_out    =   wbm_sm_write_rty_cnt_exp_out ;

assign  pciu_wbm_adr_o       =   wbm_sm_adr_out ;
assign  pciu_wbm_dat_o       =   wbm_sm_mdata_out ;
assign  pciu_wbm_cyc_o       =   wbm_sm_cyc_out ;
assign  pciu_wbm_stb_o       =   wbm_sm_stb_out ;
assign  pciu_wbm_we_o        =   wbm_sm_we_out ;
assign  pciu_wbm_cti_o       =   wbm_sm_cti_out ;
assign  pciu_wbm_bte_o       =   wbm_sm_bte_out ;
assign  pciu_wbm_sel_o       =   wbm_sm_sel_out ;

// pciw_pcir fifo outputs

// pciw_fifo_outputs:
wire [31:0] fifos_pciw_addr_data_out ;
wire [3:0]  fifos_pciw_cbe_out ;
wire [3:0]  fifos_pciw_control_out ;
wire        fifos_pciw_three_left_out ;
wire        fifos_pciw_two_left_out ;
wire        fifos_pciw_almost_full_out ;
wire        fifos_pciw_full_out ;
wire        fifos_pciw_almost_empty_out ;
wire        fifos_pciw_empty_out ;
wire        fifos_pciw_transaction_ready_out ;

assign  pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt;

// pcir_fifo_outputs
wire [31:0] fifos_pcir_data_out ;
wire [3:0]  fifos_pcir_be_out ;
wire [3:0]  fifos_pcir_control_out ;
wire        fifos_pcir_almost_empty_out ;
wire        fifos_pcir_empty_out ;

// delayed transaction logic outputs