pci_wbw_wbr_fifos.v

用verilog编写的pci——rtl级。

wire wbw_empty ;
wire wbr_empty ;

assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;

// clear wires for fifos
wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous

/*-----------------------------------------------------------------------------------------------------------
Definitions of wires for connecting RAM instances
-----------------------------------------------------------------------------------------------------------*/
wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;

wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;

/*-----------------------------------------------------------------------------------------------------------
Fifo output assignments - each ram port provides data for different fifo
-----------------------------------------------------------------------------------------------------------*/
assign wbw_control_out = dpram_portB_output[39:36] ;
assign wbr_control_out = dpram_portA_output[39:36] ;

assign wbw_cbe_out     = dpram_portB_output[35:32] ;
assign wbr_be_out      = dpram_portA_output[35:32] ;

assign wbw_addr_data_out = dpram_portB_output[31:0] ;
assign wbr_data_out      = dpram_portA_output[31:0] ;

`ifdef WB_RAM_DONT_SHARE

    /*-----------------------------------------------------------------------------------------------------------
    Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
    accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
    that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
    write port is always port a and read port is port b.
    -----------------------------------------------------------------------------------------------------------*/

    /*-----------------------------------------------------------------------------------------------------------
    Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
    -----------------------------------------------------------------------------------------------------------*/
    /*
    wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
    wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
    */

    // compose complete port addresses
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;

    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;

    wire wbw_read_enable = 1'b1 ;
    wire wbr_read_enable = 1'b1 ;

    `ifdef PCI_BIST
    wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
    wire mbist_si_i_internal = mbist_so_o_internal ;
    `endif

    // instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(wbw_whole_waddr),
        .di_a(dpram_portA_input),
        .do_a(),

        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(wbw_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbw_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o_internal),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(pci_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(wbr_wallow),
        .oe_a(1'b1),
        .addr_a(wbr_whole_waddr),
        .di_a(dpram_portB_input),
        .do_a(),

        .clk_b(wb_clock_in),
        .rst_b(reset_in),
        .ce_b(wbr_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(wbr_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portA_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i_internal),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`else // RAM blocks sharing between two fifos

    /*-----------------------------------------------------------------------------------------------------------
    Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
    case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
    -----------------------------------------------------------------------------------------------------------*/
    /*-----------------------------------------------------------------------------------------------------------
    Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
    addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
    must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;

    /*-----------------------------------------------------------------------------------------------------------
    Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
    on both sides.
    Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;

    /*-----------------------------------------------------------------------------------------------------------
    Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;

    wire portA_enable      = 1'b1 ;

    wire portB_enable      = 1'b1 ;

    // instantiate RAM for these two fifos
    pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(portA_enable),
        .we_a(wbw_wallow),
        .oe_a(1'b1),
        .addr_a(portA_addr),
        .di_a(dpram_portA_input),
        .do_a(dpram_portA_output),
        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(portB_enable),
        .we_b(wbr_wallow),
        .oe_b(1'b1),
        .addr_b(portB_addr),
        .di_b(dpram_portB_input),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`endif

/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
(
    .rclock_in(pci_clock_in),
    .wclock_in(wb_clock_in),
    .renable_in(wbw_renable_in),
    .wenable_in(wbw_wenable_in),
    .reset_in(reset_in),
//    .flush_in(wbw_flush_in),
    .almost_full_out(wbw_almost_full_out),
    .full_out(wbw_full_out),
    .empty_out(wbw_empty),
    .waddr_out(wbw_waddr),
    .raddr_out(wbw_raddr),
    .rallow_out(wbw_rallow),
    .wallow_out(wbw_wallow)
);

pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
(   .rclock_in(wb_clock_in),
    .wclock_in(pci_clock_in),
    .renable_in(wbr_renable_in),
    .wenable_in(wbr_wenable_in),
    .reset_in(reset_in),
    .flush_in(wbr_flush_in),
    .empty_out(wbr_empty),
    .waddr_out(wbr_waddr),
    .raddr_out(wbr_raddr),
    .rallow_out(wbr_rallow),
    .wallow_out(wbr_wallow)
);


// in and out transaction counters and grey codes
reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;

// input transaction counter increment - when last data of transaction is written to fifo
wire in_count_en  = wbw_wallow && wbw_last_in ;

// output transaction counter increment - when last data is on top of fifo and read from it
wire out_count_en = wbw_renable_in && wbw_last_out ;

// register holding grey coded count of incoming transactions
always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        inGreyCount <= #3 0 ;
    end
    else
    if (in_count_en)
        inGreyCount <= #3 inNextGreyCount ;
end

wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
reg  [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
    .data_in        (inGreyCount),
    .clk_out        (pci_clock_in),
    .sync_data_out  (pci_clk_sync_inGreyCount),
    .async_reset    (wbw_clear)
) ;

always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        pci_clk_inGreyCount <= #`FF_DELAY 0 ;
    else
        pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
end

// register holding grey coded count of outgoing transactions
always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
    begin
        outGreyCount <= #`FF_DELAY 0 ;
    end
    else
    if (out_count_en)
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
end

// incoming transactions counter
always@(posedge wb_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_inTransactionCount <= #`FF_DELAY 1 ;
    else
    if (in_count_en)
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end

// outgoing transactions counter
always@(posedge pci_clock_in or posedge wbw_clear)
begin
    if (wbw_clear)
        wbw_outTransactionCount <= 1 ;
    else
    if (out_count_en)
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end

assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;

endmodule