pci_user_constants.v

用verilog编写的pci——rtl级。

// or GUEST implementation.
`ifdef HOST
    `ifdef NO_CNF_IMAGE
        //`define PCI_IMAGE0
    `endif
`endif

//`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5

// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
// memory space. If initial mask for an image is defined as 0, then device independent software
// won't detect base address implemented and device dependent software will have to configure
// address masks as well as base addresses!
// Don't define PCI_AMx to 24'hffff_ff for memory images! Use that just for I/O images.
`define PCI_AM0 24'hffff_f0
`define PCI_AM1 24'hffff_ff
`define PCI_AM2 24'hffff_f0
`define PCI_AM3 24'hffff_f0
`define PCI_AM4 24'hffff_f0
`define PCI_AM5 24'hffff_f0

// initial value for PCI image maping to MEMORY or IO spaces.  If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
// Device independent software sets the base addresses acording to MEMORY or IO maping!
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b1
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b0
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b0

// initial value for PCI translation addresses. The  initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images 
// are transleted to this adresses whithout access to pci_ta registers.
`define PCI_TA0 24'h0000_0
`define PCI_TA1 24'h0000_0
`define PCI_TA2 24'h0000_0
`define PCI_TA3 24'h0000_0
`define PCI_TA4 24'h0000_0
`define PCI_TA5 24'h0000_0

`define PCI_AT_EN0 1'b0
`define PCI_AT_EN1 1'b0
`define PCI_AT_EN2 1'b0
`define PCI_AT_EN3 1'b0
`define PCI_AT_EN4 1'b0
`define PCI_AT_EN5 1'b0

// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 1

// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5

//Address bar register defines the base address for each image.
//To asccess bus without Software configuration.
`define  WB_BA1	20'h0000_0
`define  WB_BA2	20'h8000_0
`define  WB_BA3	20'h0000_0
`define  WB_BA4	20'h0000_0
`define  WB_BA5	20'h0000_0

// initial value for WB image maping to MEMORY or IO spaces.  If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space.
`define  WB_BA1_MEM_IO  1'b0
`define  WB_BA2_MEM_IO  1'b0
`define  WB_BA3_MEM_IO	1'b0
`define  WB_BA4_MEM_IO	1'b0
`define  WB_BA5_MEM_IO	1'b0  

// initial value for WB image address masks. 
`define  WB_AM1 20'h8000_0
`define  WB_AM2 20'h8000_0
`define  WB_AM3 20'h0000_0
`define  WB_AM4 20'h0000_0
`define  WB_AM5 20'h0000_0

// initial value for WB translation addresses. The  initial values
// are set after reset. When ADDR_TRAN_IMPL is defined then then Images 
// are transleted to this adresses whithout access to pci_ta registers.
`define WB_TA1 20'h0000_0
`define WB_TA2 20'h0000_0
`define WB_TA3 20'h0000_0
`define WB_TA4 20'h0000_0
`define WB_TA5 20'h0000_0

`define WB_AT_EN1 1'b0
`define WB_AT_EN2 1'b0
`define WB_AT_EN3 1'b0
`define WB_AT_EN4 1'b0
`define WB_AT_EN5 1'b0

// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//When  ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
//`define ADDR_TRAN_IMPL

// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
`define WB_DECODE_FAST
//`define WB_DECODE_MEDIUM
//`define WB_DECODE_SLOW

// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'h0000_0

// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBS_OUTPUTS

/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66

/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
	Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
	Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
	together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID        16'h1895
`define HEADER_DEVICE_ID        16'h0001
`define HEADER_REVISION_ID      8'h01
`define HEADER_SUBSYS_VENDOR_ID 16'h1895
`define HEADER_SUBSYS_ID        16'h0001
`define HEADER_MAX_LAT          8'h1a
`define HEADER_MIN_GNT          8'h08

// MAX Retry counter value for WISHBONE Master state-machine
// 	This value is 8-bit because of 8-bit retry counter !!!
`define WB_RTY_CNT_MAX			8'hff

// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
`define PCI_WBM_NO_RESPONSE_CNT_DISABLE

`define PCI_WB_REV_B3
//`define PCI_WBS_B3_RTY_DISABLE

`ifdef GUEST
//    `define PCI_CPCI_HS_IMPLEMENT
//    `define PCI_SPOCI
`endif