pci_user_constants.v

用verilog编写的pci——rtl级。

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_user_constants.v"                            ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc ([e-mail])                     ////
////      - Tadej Markovic ([e-mail])                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, [e-mail]          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_user_constants.v,v $
// Revision 1.15  2004/08/19 15:27:34  mihad
// Changed minimum pci image size to 256 bytes because
// of some PC system problems with size of IO images.
//
// Revision 1.14  2004/07/07 12:45:01  mihad
// Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
// Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.
//
// Revision 1.13  2004/01/24 11:54:18  mihad
// Update! SPOCI Implemented!
//
// Revision 1.12  2003/12/28 09:54:48  fr2201
// def_wb_imagex_addr_map  defined correctly
//
// Revision 1.11  2003/12/28 09:20:00  fr2201
// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)
//
// Revision 1.10  2003/12/19 11:11:30  mihad
// Compact PCI Hot Swap support added.
// New testcases added.
// Specification updated.
// Test application changed to support WB B3 cycles.
//
// Revision 1.9  2003/08/03 18:05:06  mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.8  2003/03/14 15:31:57  mihad
// Entered the option to disable no response counter in wb master.
//
// Revision 1.7  2003/01/27 17:05:50  mihad
// Updated.
//
// Revision 1.6  2003/01/27 16:51:19  mihad
// Old files with wrong names removed.
//
// Revision 1.5  2003/01/21 16:06:56  mihad
// Bug fixes, testcases added.
//
// Revision 1.4  2002/09/30 17:22:45  mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.3  2002/08/13 11:03:53  mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.2  2002/03/05 11:53:47  mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//

// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.

`define WBW_ADDR_LENGTH 4
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 3
`define PCIR_ADDR_LENGTH 3

//`define FPGA
//`define XILINX

`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE

`ifdef FPGA
    `ifdef XILINX
        `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
        `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
        `define PCI_XILINX_RAMB4
        `define WB_XILINX_RAMB4
        //`define PCI_XILINX_DIST_RAM
        //`define WB_XILINX_DIST_RAM
    `endif
`else
    `define PCI_FIFO_RAM_ADDR_LENGTH 3      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 4       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
//    `define WB_ARTISAN_SDP
//    `define PCI_ARTISAN_SDP
//    `define PCI_VS_STP
//    `define WB_VS_STP
`endif

// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
//`define ACTIVE_HIGH_OE

// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time
//`define HOST
`define GUEST

// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
// - ENABLED Read-Only access from PCI for HOST bridges
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
`define NO_CNF_IMAGE

// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 24

// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
// access.
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
// is no access to Configuration space possible from PCI bus.
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST