pci_master32_sm.v

用verilog编写的pci——rtl级。

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_master32_sm.v"                               ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc ([e-mail])                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, [e-mail]          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_master32_sm.v,v $
// Revision 1.5  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.4  2003/01/21 16:06:56  mihad
// Bug fixes, testcases added.
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//

// module includes pci master state machine and surrounding logic

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"

module pci_master32_sm
(
    // system inputs
    clk_in,
    reset_in,
    // arbitration
    pci_req_out,
    pci_gnt_in,
    // master in/outs
    pci_frame_in,
    pci_frame_out,
    pci_frame_out_in,
    pci_frame_load_out,
    pci_frame_en_in,
    pci_frame_en_out,
    pci_irdy_in,
    pci_irdy_out,
    pci_irdy_en_out,

    // target response inputs
    pci_trdy_in,
    pci_trdy_reg_in,
    pci_stop_in,
    pci_stop_reg_in,
    pci_devsel_in,
    pci_devsel_reg_in,

    // address, data, bus command, byte enable in/outs
    pci_ad_reg_in,
    pci_ad_out,
    pci_ad_en_out,
    pci_cbe_out,
    pci_cbe_en_out,

    // other side of state machine
    address_in,
    bc_in,
    data_in,
    data_out,
    be_in,
    req_in,
    rdy_in,
    last_in,
    next_data_in,
    next_be_in,
    next_last_in,
    ad_load_out,
    ad_load_on_transfer_out,
    wait_out,
    wtransfer_out,
    rtransfer_out,
    retry_out,
    rerror_out,
    first_out,
    mabort_out,
    latency_tim_val_in
) ;

// system inputs
input   clk_in,
        reset_in ;

/*==================================================================================================================
PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
module. Enables are separate signals.
==================================================================================================================*/
// arbitration
output  pci_req_out ;

input   pci_gnt_in ;

// master in/outs
input   pci_frame_in ;
input   pci_frame_en_in ;
input   pci_frame_out_in ;

output  pci_frame_out,
        pci_frame_en_out ;

output  pci_frame_load_out ;

input   pci_irdy_in ;
output  pci_irdy_out,
        pci_irdy_en_out;

// target response inputs
input   pci_trdy_in,
        pci_trdy_reg_in,
        pci_stop_in,
        pci_stop_reg_in,
        pci_devsel_in,
        pci_devsel_reg_in ;

// address, data, bus command, byte enable in/outs
input   [31:0]  pci_ad_reg_in ;
output  [31:0]  pci_ad_out ;

reg     [31:0]  pci_ad_out ;

output          pci_ad_en_out ;

output  [3:0]   pci_cbe_out ;

reg     [3:0]   pci_cbe_out ;

output          pci_cbe_en_out ;

input   [31:0]  address_in ; // current request address input

input   [3:0]   bc_in ;      // current request bus command input

input   [31:0]  data_in ;    // current dataphase data input

output  [31:0]  data_out ;    // for read operations - current request data output

reg     [31:0]  data_out ;

input   [3:0]   be_in ;      // current dataphase byte enable inputs

input           req_in ;     // initiator cycle is requested
input           rdy_in ;     // requestor indicates that data is ready to be sent for write transaction and ready to
                            // be received on read transaction
input           last_in ;    // last dataphase in current transaction indicator

// status outputs
output wait_out,            // wait indicates to the backend that dataphases are not in progress on PCI bus
       wtransfer_out,       // on any rising clock edge that this status is 1, data is transferred - heavy constraints here
       rtransfer_out,       // registered transfer indicator - when 1 indicates that data was transfered on previous clock cycle
       retry_out,           // retry status output - when target signals a retry
       rerror_out,          // registered error output - when 1 indicates that error was signalled by a target on previous clock cycle
       first_out ,          // indicates whether or not any data was transfered in current transaction
       mabort_out;          // master abort indicator

reg wait_out ;

// latency timer value input - state machine starts latency timer whenever it starts a transaction and last is not
// asserted ( meaning burst transfer ).
input [7:0] latency_tim_val_in ;

// next data, byte enable and last inputs
input [31:0] next_data_in ;
input [3:0]  next_be_in ;
input        next_last_in ;

// clock enable for data output flip-flops - whenever data is transfered, sm loads next data to those flip flops
output       ad_load_out,
             ad_load_on_transfer_out ;

// parameters - states - one hot
// idle state
parameter S_IDLE            = 4'h1 ;

// address state
parameter S_ADDRESS         = 4'h2 ;

// transfer state - dataphases
parameter S_TRANSFER        = 4'h4 ;

// turn arround state
parameter S_TA_END          = 4'h8 ;

// change state - clock enable for sm state register
wire change_state ;
// next state for state machine
reg [3:0] next_state ;
// SM state register
reg [3:0] cur_state ;

// variables for indicating which state state machine is in
// this variables are used to reduce logic levels in case of heavily constrained PCI signals
reg sm_idle            ;
reg sm_address         ;
reg sm_data_phases     ;
reg sm_turn_arround    ;

// state machine register control logic with clock enable
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        cur_state <= #`FF_DELAY S_IDLE ;
    else
    if ( change_state )
        cur_state <= #`FF_DELAY next_state ;
end

// parameters - data selector - ad and bc lines switch between address/data and bus command/byte enable respectively
parameter SEL_ADDR_BC      = 2'b01 ;
parameter SEL_DATA_BE      = 2'b00 ;
parameter SEL_NEXT_DATA_BE = 2'b11 ;

reg [1:0] wdata_selector ;

wire u_dont_have_pci_bus = pci_gnt_in || ~pci_frame_in || ~pci_irdy_in ;    // pci master can't start a transaction when GNT is deasserted ( 1 ) or
                                                                            // bus is not in idle state ( FRAME and IRDY both 1 )
wire u_have_pci_bus      = ~pci_gnt_in && pci_frame_in && pci_irdy_in ;

// decode count enable - counter that counts cycles passed since address phase
wire        sm_decode_count_enable = sm_data_phases ;                                                               // counter is enabled when master wants to transfer
wire        decode_count_enable    = sm_decode_count_enable && pci_trdy_in && pci_stop_in && pci_devsel_in ;        // and target is not responding
wire        decode_count_load      = ~decode_count_enable ;
reg [2:0]   decode_count ;

wire decode_to = ~( decode_count[2] || decode_count[1]) ;

always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        // initial value of counter is 4
        decode_count <= #`FF_DELAY 3'h4 ;
    else
    if ( decode_count_load )
        decode_count <= #`FF_DELAY 3'h4 ;
    else
    if ( decode_count_enable )
        decode_count <= #`FF_DELAY decode_count - 1'b1 ;
end

// Bus commands LSbit indicates whether operation is a read or a write
wire do_write = bc_in[0] ;

// latency timer
reg [7:0]   latency_timer ;

wire latency_time_out     = ~(
                               (latency_timer[7] || latency_timer[6] || latency_timer[5] || latency_timer[4]) ||
                               (latency_timer[3] || latency_timer[2] || latency_timer[1] )
                             ) ;

wire latency_timer_enable = (sm_address || sm_data_phases) && ~latency_time_out ;
wire latency_timer_load   = ~sm_address && ~sm_data_phases ;

always@(posedge clk_in or posedge reset_in)
begin
    if (reset_in)
        latency_timer <= #`FF_DELAY 8'h00 ;
    else
    if ( latency_timer_load )
        latency_timer <= #`FF_DELAY latency_tim_val_in ;
    else
    if ( latency_timer_enable)         // latency timer counts down until it expires - then it stops