pci_target32_interface.v

用verilog编写的pci——rtl级。

output	[31:0]	pciw_fifo_addr_data_out ;	// address / data output signals to PCIW_FIFO
output	[3:0]	pciw_fifo_cbe_out ;			// command / byte enable signals to PCIW_FIFO
output	[3:0]	pciw_fifo_control_out ;		// control signals to PCIW_FIFO
input           pciw_fifo_three_left_in ;       // three data spaces left in PCIW_FIFO
input           pciw_fifo_two_left_in ;		// two data spaces left in PCIW_FIFO
input			pciw_fifo_almost_full_in ;	// almost full indicator from PCIW_FIFO
input			pciw_fifo_full_in ;			// full indicator from PCIW_FIFO

// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
input			wbw_fifo_empty_in ;			// empty indicator from WBW_FIFO
input			wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit


/*==================================================================================================================
Configuration space signals - from and to registers
==================================================================================================================*/
// BUS for reading and writing to configuration space registers
output	[11:0]	conf_addr_out ;	// address to configuration space when there is access to it
output	[31:0]	conf_data_out ;	// data to configuration space - for writing to registers
input	[31:0]	conf_data_in ;	// data from configuration space - for reading from registers
output	[3:0]	conf_be_out ;	// byte enables used for correct writing to configuration space
output			conf_we_out ;	// write enable control signal - 1 for writing / 0 for nothing
output			conf_re_out ;	// read enable control signal - 1 for reading / 0 for nothing

// Inputs for image control registers
input			mem_enable_in ;	// allowed access to memory mapped image
input			io_enable_in ;	// allowed access to io mapped image

// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
input			mem_io_addr_space0_in ;	// bit-0 in pci_base_addr0 register
input			mem_io_addr_space1_in ;	// bit-0 in pci_base_addr1 register
input			mem_io_addr_space2_in ;	// bit-0 in pci_base_addr2 register
input			mem_io_addr_space3_in ;	// bit-0 in pci_base_addr3 register
input			mem_io_addr_space4_in ;	// bit-0 in pci_base_addr4 register
input			mem_io_addr_space5_in ;	// bit-0 in pci_base_addr5 register
input			pre_fetch_en0_in ;	// bit-1 in pci_image_ctr0 register
input			pre_fetch_en1_in ;	// bit-1 in pci_image_ctr1 register
input			pre_fetch_en2_in ;	// bit-1 in pci_image_ctr2 register
input			pre_fetch_en3_in ;	// bit-1 in pci_image_ctr3 register
input			pre_fetch_en4_in ;	// bit-1 in pci_image_ctr4 register
input			pre_fetch_en5_in ;	// bit-1 in pci_image_ctr5 register

// Input from image registers - register values needed for decoder to work properly
input	[pci_ba0_width   - 1:0]	pci_base_addr0_in ;	// base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_base_addr1_in ; // base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_base_addr2_in ; // base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_base_addr3_in ; // base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_base_addr4_in ; // base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_base_addr5_in ; // base address from base address register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask0_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask1_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask2_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask3_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask4_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_addr_mask5_in ; // masking of base address from address mask register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr0_in ; // translation address from address translation register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr1_in ; // translation address from address translation register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr2_in ; // translation address from address translation register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr3_in ; // translation address from address translation register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr4_in ; // translation address from address translation register
input	[pci_ba1_5_width - 1:0]	pci_tran_addr5_in ; // translation address from address translation register

input			addr_tran_en0_in ;	// address translation enable bit
input			addr_tran_en1_in ;	// address translation enable bit
input			addr_tran_en2_in ;	// address translation enable bit
input			addr_tran_en3_in ;	// address translation enable bit
input			addr_tran_en4_in ;	// address translation enable bit
input			addr_tran_en5_in ;	// address translation enable bit

/*==================================================================================================================
END of input / output PORT DEFINITONS !!!
==================================================================================================================*/

// address output from address multiplexer
reg		[31:0]	address ;
// prefetch enable for access to selected image space
reg				pre_fetch_en ;

// Input addresses and image hits from address decoders - addresses are multiplexed to address
`ifdef			HOST
	`ifdef		NO_CNF_IMAGE
		`ifdef	PCI_IMAGE0	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
wire			hit0_in ;
wire	[31:0]	address0_in ;
wire			pre_fetch_en0 = pre_fetch_en0_in ;
		`else
wire			hit0_in		= 1'b0 ;
wire	[31:0]	address0_in	= 32'h0 ;
wire			pre_fetch_en0 = 1'b0 ;
		`endif
	`else
wire			hit0_in ;
wire	[31:0]	address0_in ;
wire			pre_fetch_en0 = pre_fetch_en0_in ;
	`endif
`else // GUEST
wire			hit0_in ;
wire	[31:0]	address0_in ;
wire			pre_fetch_en0 = pre_fetch_en0_in ;
`endif

wire			hit1_in ;
wire	[31:0]	address1_in ;
wire			pre_fetch_en1 = pre_fetch_en1_in ;

`ifdef		PCI_IMAGE2
wire			hit2_in ;
wire	[31:0]	address2_in ;
wire			pre_fetch_en2 = pre_fetch_en2_in ;
`else
wire			hit2_in		= 1'b0 ;
wire	[31:0]	address2_in	= 32'h0 ;
wire			pre_fetch_en2 = 1'b0 ;
`endif

`ifdef		PCI_IMAGE3
wire			hit3_in ;
wire	[31:0]	address3_in ;
wire			pre_fetch_en3 = pre_fetch_en3_in ;
`else
wire			hit3_in		= 1'b0 ;
wire	[31:0]	address3_in	= 32'h0 ;
wire			pre_fetch_en3 = 1'b0 ;
`endif

`ifdef		PCI_IMAGE4
wire			hit4_in ;
wire	[31:0]	address4_in ;
wire			pre_fetch_en4 = pre_fetch_en4_in ;
`else
wire			hit4_in		= 1'b0 ;
wire	[31:0]	address4_in	= 32'h0 ;
wire			pre_fetch_en4 = 1'b0 ;
`endif

`ifdef		PCI_IMAGE5
wire			hit5_in ;
wire	[31:0]	address5_in ;
wire			pre_fetch_en5 = pre_fetch_en5_in ;
`else
wire			hit5_in		= 1'b0 ;
wire	[31:0]	address5_in	= 32'h0 ;
wire			pre_fetch_en5 = 1'b0 ;
`endif

// Include address decoders
`ifdef			HOST
	`ifdef		NO_CNF_IMAGE
		`ifdef	PCI_IMAGE0	// if PCI bridge is HOST and IMAGE0 is assigned as general image space
	pci_pci_decoder   #(pci_ba0_width) decoder0
				   (.hit			(hit0_in),
					.addr_out		(address0_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr0_in),
					.mask_addr		(pci_addr_mask0_in),
					.tran_addr		(pci_tran_addr0_in),
					.at_en			(addr_tran_en0_in),
					.mem_io_space	(mem_io_addr_space0_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
		`endif
	`else
	pci_pci_decoder   #(pci_ba0_width) decoder0
				   (.hit			(hit0_in),
					.addr_out		(address0_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr0_in),
					.mask_addr		({pci_ba0_width{1'b1}}),
					.tran_addr		({pci_ba0_width{1'b0}}),
					.at_en			(1'b0),
					.mem_io_space	(1'b0),
					.mem_en			(mem_enable_in),
					.io_en			(1'b0)
					) ;
	`endif
`else // GUEST
	pci_pci_decoder   #(pci_ba0_width) decoder0
				   (.hit			(hit0_in),
					.addr_out		(address0_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr0_in),
					.mask_addr		({pci_ba0_width{1'b1}}),
					.tran_addr		({pci_ba0_width{1'b0}}),
					.at_en			(1'b0),
					.mem_io_space	(1'b0),
					.mem_en			(mem_enable_in),
					.io_en			(1'b0)
					) ;
`endif
	pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
				   (.hit			(hit1_in),
					.addr_out		(address1_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr1_in),
					.mask_addr		(pci_addr_mask1_in),
					.tran_addr		(pci_tran_addr1_in),
					.at_en			(addr_tran_en1_in),
					.mem_io_space	(mem_io_addr_space1_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
`ifdef		PCI_IMAGE2
	pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
				   (.hit			(hit2_in),
					.addr_out		(address2_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr2_in),
					.mask_addr		(pci_addr_mask2_in),
					.tran_addr		(pci_tran_addr2_in),
					.at_en			(addr_tran_en2_in),
					.mem_io_space	(mem_io_addr_space2_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
`endif
`ifdef		PCI_IMAGE3
	pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
				   (.hit			(hit3_in),
					.addr_out		(address3_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr3_in),
					.mask_addr		(pci_addr_mask3_in),
					.tran_addr		(pci_tran_addr3_in),
					.at_en			(addr_tran_en3_in),
					.mem_io_space	(mem_io_addr_space3_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
`endif
`ifdef		PCI_IMAGE4
	pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
				   (.hit			(hit4_in),
					.addr_out		(address4_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr4_in),
					.mask_addr		(pci_addr_mask4_in),
					.tran_addr		(pci_tran_addr4_in),
					.at_en			(addr_tran_en4_in),
					.mem_io_space	(mem_io_addr_space4_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
`endif
`ifdef		PCI_IMAGE5
	pci_pci_decoder   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
				   (.hit			(hit5_in),
					.addr_out		(address5_in),
					.addr_in		(address_in),
					.bc_in			(bc_in),
					.base_addr		(pci_base_addr5_in),
					.mask_addr		(pci_addr_mask5_in),
					.tran_addr		(pci_tran_addr5_in),
					.at_en			(addr_tran_en5_in),
					.mem_io_space	(mem_io_addr_space5_in),
					.mem_en			(mem_enable_in),
					.io_en			(io_enable_in)
					) ;
`endif

// Internal signals for image hit determination
reg				addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM

// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
//   if normal access is allowed to configuration space, then hit0 is hit0_conf
`ifdef		HOST
	`ifdef	NO_CNF_IMAGE
			parameter	hit0_conf = 1'b0 ;
	`else
			parameter	hit0_conf = 1'b1 ;	// if normal access is allowed to configuration space, then hit0 is hit0_conf
	`endif
`else // GUEST
			parameter	hit0_conf = 1'b1 ;	// if normal access is allowed to configuration space, then hit0 is hit0_conf
`endif

// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
		address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
		pre_fetch_en5 or
		pre_fetch_en4 or
		pre_fetch_en3 or
		pre_fetch_en2 or
		pre_fetch_en1 or
		pre_fetch_en0
		)
begin
	addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
	case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
	5'b10000 :
	begin
		address <= address5_in ;
		pre_fetch_en <= pre_fetch_en5 ;
	end
	5'b01000 :
	begin
		address <= address4_in ;
		pre_fetch_en <= pre_fetch_en4 ;
	end
	5'b00100 :
	begin
		address <= address3_in ;
		pre_fetch_en <= pre_fetch_en3 ;
	end
	5'b00010 :
	begin
		address <= address2_in ;
		pre_fetch_en <= pre_fetch_en2 ;
	end
	5'b00001 :
	begin
		address <= address0_in ;
		pre_fetch_en <= pre_fetch_en0 ;
	end
	default	: // IMAGE 1 is always included into PCI bridge