📄 pci_wb_master.v
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//////////////////////////////////////////////////////////////////////
//// ////
//// File name: wb_master.v ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_wb_master.v,v $
// Revision 1.6 2004/01/24 11:54:18 mihad
// Update! SPOCI Implemented!
//
// Revision 1.5 2003/10/24 09:35:40 tadejm
// Added missing signals to 2 sensitivity lists. Everything works the same as before.
//
// Revision 1.4 2003/08/21 20:56:40 tadejm
// WB Master is now WISHBONE B3 compatible.
//
// Revision 1.3 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
// Revision 1.2 2003/01/30 22:01:09 mihad
// Updated synchronization in top level fifo modules.
//
// Revision 1.1 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.7 2002/12/05 12:19:23 mihad
// *** empty log message ***
//
// Revision 1.6 2002/10/11 14:15:29 mihad
// Cleaned up non-blocking assignments in combinatinal logic statements
//
// Revision 1.5 2002/03/05 11:53:47 mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.4 2002/02/19 16:32:37 mihad
// Modified testbench and fixed some bugs
//
// Revision 1.3 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:30 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
// New project directory structure
//
//
`define WB_FSM_BITS 3 // number of bits needed for FSM states
`include "bus_commands.v"
`include "pci_constants.v"
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module pci_wb_master
( wb_clock_in, // CLK_I
reset_in, // RST_I
pci_tar_read_request,
pci_tar_address,
pci_tar_cmd,
pci_tar_be,
pci_tar_burst_ok,
pci_cache_line_size,
cache_lsize_not_zero,
wb_read_done_out,
w_attempt,
pcir_fifo_wenable_out,
pcir_fifo_data_out,
pcir_fifo_be_out,
pcir_fifo_control_out,
//pcir_fifo_renable_out, for PCI Target !!!
//pcir_fifo_data_in, for PCI Target !!!
//pcir_fifo_be_in, for PCI Target !!!
//pcir_fifo_control_in, for PCI Target !!!
//pcir_fifo_flush_out, for PCI Target !!!
//pcir_fifo_almost_empty_in, for PCI Target !!!
//pcir_fifo_empty_in, NOT used
//pcir_fifo_transaction_ready_in, NOT used
//pciw_fifo_wenable_out, for PCI Target !!!
//pciw_fifo_addr_data_out, for PCI Target !!!
//pciw_fifo_cbe_out, for PCI Target !!!
//pciw_fifo_control_out, for PCI Target !!!
pciw_fifo_renable_out,
pciw_fifo_addr_data_in,
pciw_fifo_cbe_in,
pciw_fifo_control_in,
//pciw_fifo_flush_out, NOT used
//pciw_fifo_almost_full_in, for PCI Target !!!
//pciw_fifo_full_in, for PCI Target !!!
pciw_fifo_almost_empty_in,
pciw_fifo_empty_in,
pciw_fifo_transaction_ready_in,
pci_error_sig_out,
pci_error_bc,
write_rty_cnt_exp_out,
error_source_out,
read_rty_cnt_exp_out,
wb_cyc_o,
wb_stb_o,
wb_we_o,
wb_cti_o,
wb_bte_o,
wb_sel_o,
wb_adr_o,
wb_dat_i,
wb_dat_o,
wb_ack_i,
wb_rty_i,
wb_err_i
// CYC_O,
// STB_O,
// WE_O,
// SEL_O,
// ADR_O,
// MDATA_I,
// MDATA_O,
// ACK_I,
// RTY_I,
// ERR_I,
);
/*----------------------------------------------------------------------------------------------------------------------
Various parameters needed for state machine and other stuff
----------------------------------------------------------------------------------------------------------------------*/
parameter S_IDLE = `WB_FSM_BITS'h0 ;
parameter S_WRITE = `WB_FSM_BITS'h1 ;
parameter S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ;
parameter S_READ = `WB_FSM_BITS'h3 ;
parameter S_READ_RTY = `WB_FSM_BITS'h4 ;
parameter S_TURN_ARROUND = `WB_FSM_BITS'h5 ;
/*----------------------------------------------------------------------------------------------------------------------
System signals inputs
wb_clock_in - WISHBONE bus clock input
reset_in - system reset input controlled by bridge's reset logic
----------------------------------------------------------------------------------------------------------------------*/
input wb_clock_in ;
input reset_in ;
/*----------------------------------------------------------------------------------------------------------------------
Control signals from PCI Target for READS to PCIR_FIFO
---------------------------------------------------------------------------------------------------------------------*/
input pci_tar_read_request ; // read request from PCI Target
input [31:0] pci_tar_address ; // address for requested read from PCI Target
input [3:0] pci_tar_cmd ; // command for requested read from PCI Target
input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target
input pci_tar_burst_ok ;
input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length
input cache_lsize_not_zero ;
output wb_read_done_out ; // read done and PCIR_FIFO has data ready
output w_attempt ;
reg wb_read_done_out ;
reg wb_read_done ;
/*----------------------------------------------------------------------------------------------------------------------
PCIR_FIFO control signals used for sinking data into PCIR_FIFO and status monitoring
---------------------------------------------------------------------------------------------------------------------*/
output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output
output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO
output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO
output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO
reg [31:0] pcir_fifo_data_out ;
reg pcir_fifo_wenable_out ;
reg pcir_fifo_wenable ;
reg [3:0] pcir_fifo_control_out ;
reg [3:0] pcir_fifo_control ;
/*----------------------------------------------------------------------------------------------------------------------
PCIW_FIFO control signals used for fetching data from PCIW_FIFO and status monitoring
---------------------------------------------------------------------------------------------------------------------*/
output pciw_fifo_renable_out ; // read enable for PCIW_FIFO output
input [31:0] pciw_fifo_addr_data_in ; // address and data input from PCIW_FIFO
input [3:0] pciw_fifo_cbe_in ; // command and byte_enables from PCIW_FIFO
input [3:0] pciw_fifo_control_in ; // control bus input from PCIW_FIFO
input pciw_fifo_almost_empty_in ; // almost empty status indicator from PCIW_FIFO
input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
input pciw_fifo_transaction_ready_in ; // write transaction is ready in PCIW_FIFO
reg pciw_fifo_renable_out ;
reg pciw_fifo_renable ;
/*----------------------------------------------------------------------------------------------------------------------
Control INPUT / OUTPUT signals for configuration space reporting registers !!!
---------------------------------------------------------------------------------------------------------------------*/
output pci_error_sig_out ; // When error occures (on WB bus, retry counter, etc.)
output [3:0] pci_error_bc ; // bus command at which error occured !
output write_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during write transaction!
output read_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during read transaction!
// if error_source is '0' other side didn't respond
// if error_source is '1' other side RETRIED for max retry counter value
output error_source_out ; // Signaling error source - '0' other WB side signaled error OR didn't respond
// if '1' wridge counted max value in retry counter because of RTY responds
reg pci_error_sig_out ;
reg write_rty_cnt_exp_out ;
reg read_rty_cnt_exp_out ;
reg error_source_out ;
/*----------------------------------------------------------------------------------------------------------------------
WISHBONE bus interface signals - can be connected directly to WISHBONE bus
---------------------------------------------------------------------------------------------------------------------*/
output wb_cyc_o; // cycle indicator output
output wb_stb_o; // strobe output - data is valid when strobe and cycle indicator are high
output wb_we_o; // write enable output - 1 - write operation, 0 - read operation
output [2:0] wb_cti_o; // WB B3 - cycle type identifier
output [1:0] wb_bte_o; // WB B3 - burst type
output [3:0] wb_sel_o; // Byte select outputs
output [31:0] wb_adr_o; // WISHBONE address output
input [31:0] wb_dat_i; // WISHBONE interface input data bus
output [31:0] wb_dat_o; // WISHBONE interface output data bus
input wb_ack_i; // Acknowledge input - qualifies valid data on data output bus or received data on data input bus
input wb_rty_i; // retry input - signals from WISHBONE slave that cycle should be terminated and retried later
input wb_err_i; // Signals from WISHBONE slave that access resulted in an error
reg wb_cyc_o;
reg wb_stb_o;
reg wb_we_o;
reg [2:0] wb_cti_o;
reg [1:0] wb_bte_o;
reg [3:0] wb_sel_o;
reg [31:0] wb_dat_o;
/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
LOGIC, COUNTERS, STATE MACHINE and some control register bits
=============================================================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/
reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere !
// wire for write attempt - 1 when PCI Target attempt to write and PCIW_FIFO has a write transaction ready
reg w_attempt;
always@(posedge wb_clock_in or posedge reset_in)
begin
if (reset_in)
w_attempt <= #`FF_DELAY 1'b0;
else
begin
if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in)
w_attempt <= #`FF_DELAY 1'b1;
else
if (last_data_transferred)
w_attempt <= #`FF_DELAY 1'b0;
end
end
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