pci_wb_slave_unit.v

用verilog编写的pci——rtl级。

wire [31:0] pcim_if_address_out ;
wire [3:0]  pcim_if_bc_out ;
wire [31:0] pcim_if_data_out ;
wire [3:0]  pcim_if_be_out ;
wire        pcim_if_req_out ;
wire        pcim_if_rdy_out ;
wire        pcim_if_last_out ;
wire        pcim_if_wbw_renable_out ;
wire        pcim_if_wbr_wenable_out ;
wire [31:0] pcim_if_wbr_data_out ;
wire [3:0]  pcim_if_wbr_be_out ;
wire [3:0]  pcim_if_wbr_control_out ;
wire        pcim_if_del_complete_out ;
wire        pcim_if_del_error_out ;
wire        pcim_if_del_rty_exp_out ;
wire [31:0] pcim_if_err_addr_out ;
wire [3:0]  pcim_if_err_bc_out ;
wire        pcim_if_err_signal_out ;
wire        pcim_if_err_source_out ;
wire        pcim_if_err_rty_exp_out ;
wire        pcim_if_tabort_out ;
wire        pcim_if_mabort_out ;
wire [31:0] pcim_if_next_data_out ;
wire [3:0]  pcim_if_next_be_out ;
wire        pcim_if_next_last_out ;
wire        pcim_if_posted_write_not_present_out ;



wire        pcim_sm_req_out ;
wire        pcim_sm_frame_out ;
wire        pcim_sm_frame_en_out ;
wire        pcim_sm_irdy_out ;
wire        pcim_sm_irdy_en_out ;
wire [31:0] pcim_sm_ad_out ;
wire        pcim_sm_ad_en_out ;
wire [3:0]  pcim_sm_cbe_out ;
wire        pcim_sm_cbe_en_out ;
wire        pcim_sm_ad_load_out ;
wire        pcim_sm_ad_load_on_transfer_out ;

wire        pcim_sm_wait_out ;
wire        pcim_sm_wtransfer_out ;
wire        pcim_sm_rtransfer_out ;
wire        pcim_sm_retry_out ;
wire        pcim_sm_rerror_out ;
wire        pcim_sm_first_out ;
wire        pcim_sm_mabort_out ;
wire        pcim_sm_frame_load_out ;

assign wbu_pciif_frame_load_out = pcim_sm_frame_load_out ;

assign wbu_err_addr_out     =   pcim_if_err_addr_out ;
assign wbu_err_bc_out       =   pcim_if_err_bc_out ;
assign wbu_err_signal_out   =   pcim_if_err_signal_out ;
assign wbu_err_source_out   =   pcim_if_err_source_out ;
assign wbu_err_rty_exp_out  =   pcim_if_err_rty_exp_out ;
assign wbu_tabort_rec_out   =   pcim_if_tabort_out ;
assign wbu_mabort_rec_out   =   pcim_if_mabort_out ;

assign wbu_wbw_fifo_empty_out = pcim_if_posted_write_not_present_out ;

// pci master state machine outputs
// pci interface signals
assign  wbu_pciif_req_out           =           pcim_sm_req_out ;
assign  wbu_pciif_frame_out         =           pcim_sm_frame_out ;
assign  wbu_pciif_frame_en_out      =           pcim_sm_frame_en_out ;
assign  wbu_pciif_irdy_out          =           pcim_sm_irdy_out ;
assign  wbu_pciif_irdy_en_out       =           pcim_sm_irdy_en_out ;
assign  wbu_pciif_ad_out            =           pcim_sm_ad_out ;
assign  wbu_pciif_ad_en_out         =           pcim_sm_ad_en_out ;
assign  wbu_pciif_cbe_out           =           pcim_sm_cbe_out ;
assign  wbu_pciif_cbe_en_out        =           pcim_sm_cbe_en_out ;
assign  wbu_ad_load_out             =           pcim_sm_ad_load_out ;
assign  wbu_ad_load_on_transfer_out =           pcim_sm_ad_load_on_transfer_out ;

// signals to internal of the core
wire [31:0] pcim_sm_data_out ;

// wishbone slave state machine outputs
wire [3:0]  wbs_sm_del_bc_out ;
wire        wbs_sm_del_req_out ;
wire        wbs_sm_del_done_out ;
wire        wbs_sm_del_burst_out ;
wire        wbs_sm_del_write_out ;
wire [11:0] wbs_sm_conf_offset_out ;
wire        wbs_sm_conf_renable_out ;
wire        wbs_sm_conf_wenable_out ;
wire [3:0]  wbs_sm_conf_be_out ;
wire [31:0] wbs_sm_conf_data_out ;
wire [31:0] wbs_sm_data_out ;
wire [3:0]  wbs_sm_cbe_out ;
wire        wbs_sm_wbw_wenable_out ;
wire [3:0]  wbs_sm_wbw_control_out ;
wire        wbs_sm_wbr_renable_out ;
wire        wbs_sm_wbr_flush_out ;
wire        wbs_sm_del_in_progress_out ;
wire [31:0] wbs_sm_sdata_out ;
wire        wbs_sm_ack_out ;
wire        wbs_sm_rty_out ;
wire        wbs_sm_err_out ;
wire        wbs_sm_sample_address_out ;

assign wbu_conf_offset_out  = wbs_sm_conf_offset_out ;
assign wbu_conf_renable_out = wbs_sm_conf_renable_out ;
assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ;
assign wbu_conf_be_out      = ~wbs_sm_conf_be_out ;
assign wbu_conf_data_out    = wbs_sm_conf_data_out ;

assign SDATA_O = wbs_sm_sdata_out ;
assign ACK_O   = wbs_sm_ack_out ;
assign RTY_O   = wbs_sm_rty_out ;
assign ERR_O   = wbs_sm_err_out ;


// wbw_wbr fifo outputs

// wbw_fifo_outputs:
wire [31:0] fifos_wbw_addr_data_out ;
wire [3:0]  fifos_wbw_cbe_out ;
wire [3:0]  fifos_wbw_control_out ;
wire        fifos_wbw_almost_full_out ;
wire        fifos_wbw_full_out ;
wire        fifos_wbw_empty_out ;
wire        fifos_wbw_transaction_ready_out ;

// wbr_fifo_outputs
wire [31:0] fifos_wbr_data_out ;
wire [3:0]  fifos_wbr_be_out ;
wire [3:0]  fifos_wbr_control_out ;
wire        fifos_wbr_empty_out ;

// address multiplexer outputs
wire [5:0]  amux_hit_out ;
wire [31:0] amux_address_out ;

// delayed transaction logic outputs
wire [31:0] del_sync_addr_out ;
wire [3:0]  del_sync_be_out ;
wire        del_sync_we_out ;
wire        del_sync_comp_req_pending_out ;
wire        del_sync_comp_comp_pending_out ;
wire        del_sync_req_req_pending_out ;
wire        del_sync_req_comp_pending_out ;
wire [3:0]  del_sync_bc_out ;
wire        del_sync_status_out ;
wire        del_sync_comp_flush_out ;
wire        del_sync_burst_out ;

assign wbu_del_read_comp_pending_out = del_sync_comp_comp_pending_out ;

// delayed write storage output
wire [31:0] del_write_data_out ;

// config. cycle address decoder output
wire [31:0] ccyc_addr_out ;


// WISHBONE slave interface inputs
wire [4:0]  wbs_sm_hit_in                   =       amux_hit_out[5:1] ;
wire        wbs_sm_conf_hit_in              =       amux_hit_out[0]   ;
wire [4:0]  wbs_sm_map_in                   =       wbu_map_in[5:1]        ;
wire [4:0]  wbs_sm_pref_en_in               =       wbu_pref_en_in[5:1]    ;
wire [4:0]  wbs_sm_mrl_en_in                =       wbu_mrl_en_in[5:1]     ;
wire [31:0] wbs_sm_addr_in                  =       amux_address_out ;
wire [3:0]  wbs_sm_del_bc_in                =       del_sync_bc_out  ;
wire        wbs_sm_del_req_pending_in       =       del_sync_req_req_pending_out ;
wire        wbs_sm_wb_del_comp_pending_in   =       del_sync_req_comp_pending_out ;
wire        wbs_sm_pci_drcomp_pending_in    =       wbu_pci_drcomp_pending_in ;
wire        wbs_sm_del_write_in             =       del_sync_we_out ;
wire        wbs_sm_del_error_in             =       del_sync_status_out ;
wire [31:0] wbs_sm_del_addr_in              =       del_sync_addr_out ;
wire [3:0]  wbs_sm_del_be_in                =       del_sync_be_out ;
wire [31:0] wbs_sm_conf_data_in             =       wbu_conf_data_in ;
wire        wbs_sm_wbw_almost_full_in       =       fifos_wbw_almost_full_out ;
wire        wbs_sm_wbw_full_in              =       fifos_wbw_full_out ;
wire [3:0]  wbs_sm_wbr_be_in                =       fifos_wbr_be_out ;
wire [31:0] wbs_sm_wbr_data_in              =       fifos_wbr_data_out ;
wire [3:0]  wbs_sm_wbr_control_in           =       fifos_wbr_control_out ;
wire        wbs_sm_wbr_empty_in             =       fifos_wbr_empty_out ;
wire        wbs_sm_pciw_empty_in            =       wbu_pciw_empty_in ;
wire        wbs_sm_lock_in                  =       ~wbu_master_enable_in ;
wire		wbs_sm_cache_line_size_not_zero	=		wbu_cache_line_size_not_zero ;
wire        wbs_sm_cyc_in                   =       CYC_I ;
wire        wbs_sm_stb_in                   =       STB_I ;
wire        wbs_sm_we_in                    =       WE_I  ;
wire [3:0]  wbs_sm_sel_in                   =       SEL_I ;
wire [31:0] wbs_sm_sdata_in                 =       SDATA_I ;
wire        wbs_sm_cab_in                   =       CAB_I ;
wire [31:0] wbs_sm_ccyc_addr_in             =       ccyc_addr_out ;
wire        wbs_sm_init_complete_in         =       wb_init_complete_in ;

// WISHBONE slave interface instantiation
pci_wb_slave wishbone_slave(
                        .wb_clock_in              (wb_clock_in) ,
                        .reset_in                 (reset_in) ,
                        .wb_hit_in                (wbs_sm_hit_in) ,
                        .wb_conf_hit_in           (wbs_sm_conf_hit_in) ,
                        .wb_map_in                (wbs_sm_map_in) ,
                        .wb_pref_en_in            (wbs_sm_pref_en_in) ,
                        .wb_mrl_en_in             (wbs_sm_mrl_en_in) ,
                        .wb_addr_in               (wbs_sm_addr_in),
                        .del_bc_in                (wbs_sm_del_bc_in),
                        .wb_del_req_pending_in    (wbs_sm_del_req_pending_in),
                        .wb_del_comp_pending_in   (wbs_sm_wb_del_comp_pending_in),
                        .pci_drcomp_pending_in    (wbs_sm_pci_drcomp_pending_in),
                        .del_bc_out               (wbs_sm_del_bc_out),
                        .del_req_out              (wbs_sm_del_req_out),
                        .del_done_out             (wbs_sm_del_done_out),
                       	.del_burst_out            (wbs_sm_del_burst_out),
                        .del_write_out            (wbs_sm_del_write_out),
                        .del_write_in             (wbs_sm_del_write_in),
                        .del_error_in             (wbs_sm_del_error_in),
                        .wb_del_addr_in           (wbs_sm_del_addr_in),
                        .wb_del_be_in             (wbs_sm_del_be_in),
                        .wb_conf_offset_out       (wbs_sm_conf_offset_out),
                        .wb_conf_renable_out      (wbs_sm_conf_renable_out),
                        .wb_conf_wenable_out      (wbs_sm_conf_wenable_out),
                        .wb_conf_be_out           (wbs_sm_conf_be_out),
                        .wb_conf_data_in          (wbs_sm_conf_data_in),
                        .wb_conf_data_out         (wbs_sm_conf_data_out),
                        .wb_data_out              (wbs_sm_data_out),
                        .wb_cbe_out               (wbs_sm_cbe_out),
                        .wbw_fifo_wenable_out     (wbs_sm_wbw_wenable_out),
                        .wbw_fifo_control_out     (wbs_sm_wbw_control_out),
                        .wbw_fifo_almost_full_in  (wbs_sm_wbw_almost_full_in),
                        .wbw_fifo_full_in         (wbs_sm_wbw_full_in),
                        .wbr_fifo_renable_out     (wbs_sm_wbr_renable_out),
                        .wbr_fifo_be_in           (wbs_sm_wbr_be_in),
                        .wbr_fifo_data_in         (wbs_sm_wbr_data_in),
                        .wbr_fifo_control_in      (wbs_sm_wbr_control_in),
                        .wbr_fifo_flush_out       (wbs_sm_wbr_flush_out),
                        .wbr_fifo_empty_in        (wbs_sm_wbr_empty_in),
                        .pciw_fifo_empty_in       (wbs_sm_pciw_empty_in),
                        .wbs_lock_in              (wbs_sm_lock_in),
                        .init_complete_in         (wbs_sm_init_complete_in),
                        .cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
                        .del_in_progress_out      (wbs_sm_del_in_progress_out),
                        .ccyc_addr_in             (wbs_sm_ccyc_addr_in),
                        .sample_address_out       (wbs_sm_sample_address_out),
                        .CYC_I                    (wbs_sm_cyc_in),
                        .STB_I                    (wbs_sm_stb_in),
                        .WE_I                     (wbs_sm_we_in),
                        .SEL_I                    (wbs_sm_sel_in),
                        .SDATA_I                  (wbs_sm_sdata_in),
                        .SDATA_O                  (wbs_sm_sdata_out),
                        .ACK_O                    (wbs_sm_ack_out),
                        .RTY_O                    (wbs_sm_rty_out),
                        .ERR_O                    (wbs_sm_err_out),
                        .CAB_I                    (wbs_sm_cab_in)
                       );

// wbw_wbr_fifos inputs
// WBW_FIFO inputs
wire        fifos_wbw_wenable_in        =       wbs_sm_wbw_wenable_out;
wire [31:0] fifos_wbw_addr_data_in      =       wbs_sm_data_out ;
wire [3:0]  fifos_wbw_cbe_in            =       wbs_sm_cbe_out ;
wire [3:0]  fifos_wbw_control_in        =       wbs_sm_wbw_control_out ;
wire        fifos_wbw_renable_in        =       pcim_if_wbw_renable_out ;

//wire        fifos_wbw_flush_in          =       1'b0 ; flush for write fifo not used

// WBR_FIFO inputs
wire        fifos_wbr_wenable_in        =       pcim_if_wbr_wenable_out ;
wire [31:0] fifos_wbr_data_in           =       pcim_if_wbr_data_out ;
wire [3:0]  fifos_wbr_be_in             =       pcim_if_wbr_be_out ;
wire [3:0]  fifos_wbr_control_in        =       pcim_if_wbr_control_out ;
wire        fifos_wbr_renable_in        =       wbs_sm_wbr_renable_out ;
wire        fifos_wbr_flush_in          =       wbs_sm_wbr_flush_out || del_sync_comp_flush_out ;

// WBW_FIFO and WBR_FIFO instantiation
pci_wbw_wbr_fifos fifos
(
    .wb_clock_in               (wb_clock_in),
    .pci_clock_in              (pci_clock_in),
    .reset_in                  (reset_in),
    .wbw_wenable_in            (fifos_wbw_wenable_in),
    .wbw_addr_data_in          (fifos_wbw_addr_data_in),
    .wbw_cbe_in                (fifos_wbw_cbe_in),
    .wbw_control_in            (fifos_wbw_control_in),
    .wbw_renable_in            (fifos_wbw_renable_in),
    .wbw_addr_data_out         (fifos_wbw_addr_data_out),
    .wbw_cbe_out               (fifos_wbw_cbe_out),
    .wbw_control_out           (fifos_wbw_control_out),
//    .wbw_flush_in              (fifos_wbw_flush_in),        // flush for write fifo not used
    .wbw_almost_full_out       (fifos_wbw_almost_full_out),
    .wbw_full_out              (fifos_wbw_full_out),
    .wbw_empty_out             (fifos_wbw_empty_out),
    .wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
    .wbr_wenable_in            (fifos_wbr_wenable_in),
    .wbr_data_in               (fifos_wbr_data_in),
    .wbr_be_in                 (fifos_wbr_be_in),
    .wbr_control_in            (fifos_wbr_control_in),