📄 altsyncram_gaa2.tdf

📁 FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl
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			INIT_FILE = "./DATA/sin_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a5 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "./DATA/sin_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a6 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "./DATA/sin_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a7 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "./DATA/sin_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	data_a[7..0]	: NODE;
	wren_a	: NODE;

BEGIN 
	ram_block3a[7..0].clk0 = clock0;
	ram_block3a[7..0].clk1 = clock1;
	ram_block3a[0].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[1].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[2].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[3].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[4].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[5].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[6].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[7].portaaddr[] = ( B"0000000", address_a[8..0]);
	ram_block3a[0].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[0..0]);
	ram_block3a[1].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[1..1]);
	ram_block3a[2].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[2..2]);
	ram_block3a[3].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[3..3]);
	ram_block3a[4].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[4..4]);
	ram_block3a[5].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[5..5]);
	ram_block3a[6].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[6..6]);
	ram_block3a[7].portadatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", data_a[7..7]);
	ram_block3a[7..0].portawe = wren_a;
	ram_block3a[0].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[1].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[2].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[3].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[4].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[5].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[6].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[7].portbaddr[] = ( B"0000000", address_b[8..0]);
	ram_block3a[0].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[0..0]);
	ram_block3a[1].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[1..1]);
	ram_block3a[2].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[2..2]);
	ram_block3a[3].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[3..3]);
	ram_block3a[4].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[4..4]);
	ram_block3a[5].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[5..5]);
	ram_block3a[6].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[6..6]);
	ram_block3a[7].portbdatain[] = ( B"00000000000000000000000000000000000000000000000000000000000000000000000", data_b[7..7]);
	ram_block3a[7..0].portbrewe = wren_b;
	data_a[] = VCC;
	q_a[] = ( ram_block3a[7].portadataout[0..0], ram_block3a[6].portadataout[0..0], ram_block3a[5].portadataout[0..0], ram_block3a[4].portadataout[0..0], ram_block3a[3].portadataout[0..0], ram_block3a[2].portadataout[0..0], ram_block3a[1].portadataout[0..0], ram_block3a[0].portadataout[0..0]);
	q_b[] = ( ram_block3a[7].portbdataout[0..0], ram_block3a[6].portbdataout[0..0], ram_block3a[5].portbdataout[0..0], ram_block3a[4].portbdataout[0..0], ram_block3a[3].portbdataout[0..0], ram_block3a[2].portbdataout[0..0], ram_block3a[1].portbdataout[0..0], ram_block3a[0].portbdataout[0..0]);
	wren_a = GND;
END;
--VALID FILE
上一页 12
💿 文件大小 803 K
👤 上传用户 wyly
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#QUIRTE #FPGA #vhdl #数字移相器
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