add.vhd

来自「FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl」· VHDL 代码 · 共 54 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add is
  port(poin : in std_logic_vector(31 downto 0);
        clk : in std_logic;
          en: in std_logic;
        sinout,stand:out std_logic_vector(8 downto 0));
end add;

architecture add_n of add is
signal i: std_logic_vector(31 downto 0);
signal flag :std_logic;
signal temp : std_logic_vector(8 downto 0);
signal change : std_logic;
--signal temp1,temp2:std_logic_vector(8 downto 0);
begin

p2 : process(en)
begin
 	if en'event and en = '1' then 
		if (poin( 8 downto 0) >= 100) then
			temp <= "001100011";	
		else 
			temp <= poin(8 downto 0);
		end if; 
		if poin(31 downto 28)="0000" then
			change <= '1';
		else 
			change <= '0';
		end if;
	end if;
end process p2;
p1:process(clk, change)
begin
--if poin(31 downto 28)="0000" then
if change = '1' then 
  if clk'event and clk='1' then
    if i=100 then
      i<="00000000000000000000000000000000";
     else 
     stand<=i(8 downto 0);
     i<=i+1;
       if (temp+i(8 downto 0))>=100 then
       	sinout<=temp+i(8 downto 0)-100;
       else 
       	sinout<=temp+i(8 downto 0);
       end if;
     end if; 
  end if;
end if;
end process p1;
end add_n;