piso.vhd

来自「FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;

entity piso is 
  port (load : in std_logic;
        clock:in std_logic;
        po:out std_logic_vector(31 downto 0);
        sI:IN std_logic;
		en: out std_logic);
end piso;
architecture behave of piso is
begin 
process(clock,load)
variable i:integer range 0 to 31;
begin
  if load='1' then
    i:=0;
	en <= '1';
  else
	en <= '0';
  	if CLOCK'EVENT AND CLOCK='0' then
		po(i) <= si;
  		i:=i+1;
	end if;
  end if;
end process;
end;