piso.tan.qmsg

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout\[0\] sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\] 9.052 ns memory " "Info: tco from clock clk to destination pin fout\[0\] through memory sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\] is 9.052 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.756 ns + Longest memory " "Info: + Longest clock path from clock clk to source memory is 2.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 85; CLK Node = 'clk'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.708 ns) 2.756 ns sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\] 2 MEM M4K_X13_Y10 1 " "Info: 2: + IC(0.579 ns) + CELL(0.708 ns) = 2.756 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.287 ns" { clk sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.99 % " "Info: Total cell delay = 2.177 ns ( 78.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 21.01 % " "Info: Total interconnect delay = 0.579 ns ( 21.01 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.756 ns" { clk sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.646 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\] 1 MEM M4K_X13_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[0\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.418 ns) + CELL(2.124 ns) 5.646 ns fout\[0\] 2 PIN PIN_74 0 " "Info: 2: + IC(3.418 ns) + CELL(2.124 ns) = 5.646 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'fout\[0\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "5.542 ns" { sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] fout[0] } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.228 ns 39.46 % " "Info: Total cell delay = 2.228 ns ( 39.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.418 ns 60.54 % " "Info: Total interconnect delay = 3.418 ns ( 60.54 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "5.646 ns" { sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] fout[0] } "NODE_NAME" } } }  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.756 ns" { clk sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "5.646 ns" { sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] fout[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin altera_internal_jtag~TDO to destination pin altera_reserved_tdo is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 3.372 ns register " "Info: th for register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] (data pin = altera_internal_jtag~TMSUTAP, clock pin = altera_internal_jtag~TCKUTAP) is 3.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.875 ns + Longest register " "Info: + Longest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 205 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 205; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.164 ns) + CELL(0.711 ns) 4.875 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] 2 REG LC_X8_Y10_N3 3 " "Info: 2: + IC(4.164 ns) + CELL(0.711 ns) = 4.875 ns; Loc. = LC_X8_Y10_N3; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.875 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.58 % " "Info: Total cell delay = 0.711 ns ( 14.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.164 ns 85.42 % " "Info: Total interconnect delay = 4.164 ns ( 85.42 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.875 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.518 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(0.309 ns) 1.518 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] 2 REG LC_X8_Y10_N3 3 " "Info: 2: + IC(1.209 ns) + CELL(0.309 ns) = 1.518 ns; Loc. = LC_X8_Y10_N3; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.518 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 20.36 % " "Info: Total cell delay = 0.309 ns ( 20.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.209 ns 79.64 % " "Info: Total interconnect delay = 1.209 ns ( 79.64 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.518 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } }  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.875 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.518 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk pout\[3\] sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\] 7.546 ns memory " "Info: Minimum tco from clock clk to destination pin pout\[3\] through memory sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\] is 7.546 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.756 ns + Shortest memory " "Info: + Shortest clock path from clock clk to source memory is 2.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 85; CLK Node = 'clk'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.708 ns) 2.756 ns sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.579 ns) + CELL(0.708 ns) = 2.756 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "1.287 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 78.99 % " "Info: Total cell delay = 2.177 ns ( 78.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 21.01 % " "Info: Total interconnect delay = 0.579 ns ( 21.01 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.756 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.140 ns + Shortest memory pin " "Info: + Shortest memory to pin delay is 4.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\] 1 MEM M4K_X13_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|altsyncram_gaa2:altsyncram1\|q_a\[3\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] } "NODE_NAME" } } } { "F:/zhf/piso/db/altsyncram_gaa2.tdf" "" "" { Text "F:/zhf/piso/db/altsyncram_gaa2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.928 ns) + CELL(2.108 ns) 4.140 ns pout\[3\] 2 PIN PIN_56 0 " "Info: 2: + IC(1.928 ns) + CELL(2.108 ns) = 4.140 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'pout\[3\]'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.036 ns" { sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] pout[3] } "NODE_NAME" } } } { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns 53.43 % " "Info: Total cell delay = 2.212 ns ( 53.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.928 ns 46.57 % " "Info: Total interconnect delay = 1.928 ns ( 46.57 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.140 ns" { sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] pout[3] } "NODE_NAME" } } }  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.756 ns" { clk sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] } "NODE_NAME" } } } { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "4.140 ns" { sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] pout[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Shortest " "Info: Shortest tpd from source pin altera_internal_jtag~TDO to destination pin altera_reserved_tdo is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y6_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_90 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/EDA/piso/db/piso_cmp.qrpt" "" "" { Report "G:/EDA/piso/db/piso_cmp.qrpt" Compiler "piso" "UNKNOWN" "V1" "G:/EDA/piso/db/piso.quartus_db" { Floorplan "" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } }  } 0}